Cost-Optimized Portfolio
Broadest Cost-Optimized Portfolio
Whether designing an HDMI interface for 4K2K display, an RX beam former for portable ultrasound, or an entire mobile backhaul SoC solution, applications demanding low cost, low density programmable solutions have come to expect a broad feature set for varying levels of integration, performance and power.
The Xilinx Cost-Optimized Portfolio comprises four families that are optimized for specific capabilities:
- Spartan®-6 FPGA for I/O optimization
- Spartan-7 FPGAs for I/O optimization with the highest performance-per-watt
- Artix®-7 FPGAs for transceiver optimization and highest DSP bandwidth
- Zynq®-7000 SoCs for system optimization with scalable processor integration
I/O Optimized
- Any-to-Any Connectivity
- Sensor Fusion
I/O Optimized
- Any-to-Any Connectivity
- Sensor Fusion
- Precision Control
- Safety and Security
Transceiver Optimized
- Any-to-Any Connectivity
- Sensor Fusion
- Precision Control
- Safety and Security
- Image Processing
System Optimized
- Any-to-Any Connectivity
- Sensor Fusion
- Precision Control
- Safety and Security
- Image Processing
- Analytics and Cloud
Cost-Optimized Portfolio Maximum Capacity Comparison
| Spartan-6 FPGA |
Spartan-7 FPGA | Artix-7 FPGA | Zynq SoCs Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, Z-7020 |
|
| Logic Cells | 150K | 100K | 215K | 85K |
| Block RAM | 4.8 Mb | 4.2 Mb | 13 Mb | 4.9 Mb |
| DSP Slices | 180 | 160 | 740 | 220 |
| Transceiver Count | 8 | -- | 16 | 4 |
| Transceiver Speed | 3.2 Gb/s | -- | 6.6 Gb/s | 6.6 Gb/s (Z-7012S, Z-7015) |
| Memory Interface (DDR3) | 800 Mb/s |
800 Mb/s | 1,066 Mb/s | 1,066 Mb/s |
| PCI Express Interface | Gen1x1 | -- | Gen2x4 | Gen2x4 (Z-7012S, Z-7015) |
| Analog Mixed Signal (AMS) / XDAC | -- | Dual 12-bit 1MSPS ADC with on-chip temp/supply sensors | ||
| I/O Pins | 576 | 400 | 500 | 328 |
| I/O Standard Support (40+ protocols supported) |
LVDS, Mini-LVDS, Diff HSTL, Diff SSTL, DisplayPort, XAUI, CPRI/OBSAI, V-by-One, Triple Rate SDI, 6G-SDI (Artix-7 FPGA/Zynq-7000 SoCs) |
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Additional Zynq-7000 SoC Specifications
| Processor Core | Single- or dual-core ARM® Cortex™-A9 MPCore™ (up to 866MHz) NEON™ & Single/Double Precision Floating Point for each processor L1: 32 KB Instruction/32 KB Data per processor |
| Memory Interfaces | DDR3, DDR3L, DDR2, LPDDR2, 2x Quad-SPI, NAND, NOR |
| Peripherals | 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO, 2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO |
Developer Zone
For FPGA designers looking to shorten design time and ensure scalability and re-use, Xilinx provides a comprehensive suite of solutions ranging from C-based design abstractions to IP plug-and-play to address bottlenecks in hardware development, system-level integration, and implementation.
