Versal AI Core Series VCK190 Evaluation Kit

VCK190 is the first Versal AI Core series evaluation kit, enabling designers to develop solutions using AI and DSP engines capable of delivering over 100X greater compute performance compared to current server class CPUs. With a breadth of connectivity options and standardized development flows, the VCK190 kit features the VC1902 Versal AI Core series ACAP, providing the portfolio's highest AI inference and signal processing throughput for cloud, network, and edge applications.

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Overview

Xilinx is currently offering EK-VCK190-G-ED. This encryption disabled (-ED) evaluation kit does not support the following features below:

  • Arm® v8 cryptography extensions
  • Cryptographic accelerator
  • Secure Boot

Product Description

The VCK190 kit is the first Versal™ AI Core series evaluation kit, enabling designers to develop solutions using AI and DSP engines capable of delivering over 100X greater compute performance than today's server-class CPUs.

With a breadth of connectivity options and standardized development flows, the VCK190 kit features the Versal AI Core series VC1902 device, providing the portfolio's highest AI inference and signal processing throughput.

The VCK190 kit is an ideal platform supporting high throughput AI inference and signal processing applications from the cloud to edge, such as:

  • Data center compute
  • 5G radio & beamforming (DFE)
  • Cable-access (Head-End)
  • Wireless test equipment
  • Automotive/ADAS prototyping
  • A&D radar, early warning

Key Features & Benefits

Evaluate Versal AI Core Series Capabilities

  • Equipped with Versal ACAP VC1902 production silicon
  • AI and DSP Engines providing 100X greater compute over today’s server-class CPUs
  • Pre-built partner reference designs for rapid prototyping

Breadth of Connectivity Options for Rapid Application Development

  • PCIe® Gen4 interface for high compute performance markets
  • HDMI for video processing applications
  • SFP28 and QSFP28 optical interfaces and RJ-45 Ethernet port for networking
  • DDR4 and LPDDR4 memory interfaces
  • FMC expansion connectors supporting a variety of optional plug-in cards including camera sensors and displays

Co-Optimized Tools and Debug Method

  • Vivado® Design Suite, Vitis™ unified software platform, Vitis AI, AI Engine tools

Featured Xilinx Devices

Featuring the Versal VC1902 ACAP

AI Engines 400
DSP Engines 1,968
System Logic Cells (K) 1,968
LUTs 899,840
Application Processing Unit Dual-Core Arm® Cortex®-A72
Real-Time Processing Unit Dual-Core Arm Cortex-R5F
Maximum I/O Pins 770
Programmable NoC Ports 28
Integrated Memory Controllers 4
versal-chip

Product Information

Specifications

Board Features

Featuring the Versal™ VC1902 ACAP

Versal VC1902 ACAP
Board Specifications Value
Length 7.477 in
Height 9.5 in
PCB Thickness (+/-8%) 0.066 in
Operating Environmental Temperature 0°C to +45°C
Storage Environmental Temperature –25°C to +60°C
Configuration
JTAG Yes
QSPI Yes
Micro SD 2
Memory
DDR4 DIMM 8GB
LPDDR4 Component 8GB (4x16Gb)
Micro SD Socket 16GB
Control I/O
User Pushbuttons 6
DIP Switches 4
User LEDs 4
SYSMON Yes
System Controller Yes
PMBUS Yes
Expansion Connectors
VITA 57.4 FMC+ (12 GTYs per connector) 2
PCIe® Gen4 x8 1
Communication & Networking
UART to USB Bridge 1
CAN-FD Header 1
RJ-45 Tri-Speed Ethernet Connectors 3
SFP28 2
QSFP28 1
Display
HDMI Video Output 1
HDMI Video Input 1
Clocking
Programmable DDR4 DIMM 1
Programmable LPDDR4 Component 2
PCIe Reference Clock 1
HDMI 1
Programmable zSFP 1
Programmable HSDP 1
Programmable 1588 eCPRI 4
Programmable System Controller 1
Power
180V (12V) Power Supply Yes
Power on Reset Yes
What's Inside

What's Inside the Box

Featuring the Versal™ VC1902 ACAP

vck190-whats-inside

Resources

Documentation
Default Default Title Document Type Date
Tools & IP

Design Tools

Name Description License Type
Vivado Design Suite Design Edition The Xilinx® Vivado® Design Suite is a revolutionary IP and System Centric design environment built from the ground up to accelerate the design for FPGAs and SoCs. Node locked device-locked to the XCVC1902 Versal AI Core device, with one year of updates
VITIS Full suite of tools for embedded software development and debug targeting Xilinx platforms. Free
PetaLinux Tools Configure, build, and deploy Linux operating system to Xilinx platforms. Free

Quick Start Guide

Name Description License Type
VCK190 Quick Start Guide Pre-work, board setup, and files needed to boot and run designs on the VCK190 board. You will need to download files and applications to interface to the boards. No installation or knowledge of the Xilinx tools are required to run these on the VCK190. Free
Prebuilt PetaLinux Images List of prebuilt Linux images that can be used with the Quick Start Guide. Free

Xilinx Targeted Reference Designs

Name Description Version License Type
VCK190 Base Targeted Reference Design The Versal Base Targeted Reference Design targets VCK190 Evaluation board. It supports 3 platforms each with different set of receiver I/Os.  The platform captures video from the receiver  and displays it on a Jupyter Notebook or a HDMI monitor. Computer Vision or Machine learning accelerator functions can also be added to these platforms.

2020.2

2021.1

IP Licenses Included 
VCK190 Ethernet Targeted Reference Designs Reference designs that showcase the value proposition of Versal devices. Platform designs include 10G/25G/100G MRMAC Ethernet based IP targeted for various markets. The user can use these designs as is or modify it per application requirements. 2021.1 Includes Evaluation Licenses
Versal Restart Targeted Reference Design The Versal System and Subsystem Restart TRD (VSSR TRD), also referred to as Versal Restart TRD, demonstrates how to restart various components of a system. It also showcases the liveliness of a subsystem while another subsystem is undergoing restart.  The TRD consists of a baseline Vivado design, Petalinux, Jupyter notebooks and other software components to demonstrate different restart scenarios. 2021.1

2020.2 
(Login Required)
Includes Evaluation Licenses
The Versal Subsystem Restart TRD demonstrates how to restart one processor subsystem without disturbing the other subsystems in the design.  The TRD consists of a baseline design and a compression design, software drivers, Petalinux, and Jupyter notebooks to demonstrate different restart scenarios. 2020.2 
(Login Required)
Free

Third Party Reference Designs

Name Description License Type
Third Party Reference Designs List of reference designs built by Xilinx Partners, which may include third party IP or tool flows targeting Versal ACAP devices. Includes IP Evaluation licenses

Example Designs

Name Description License Type
Versal Example Designs List of many available example designs showcasing particular IP, Silicon features or tool flows targeting Versal ACAP devices. Includes IP Evaluation licenses

PetaLinux Board Support Package (BSP)

Name Description License Type
VCK190 PetaLinux BSP List of PetaLinux Tools and BSP available for VCK190 Evaluation Kit. Includes IP Evaluation licenses
Prebuilt PetaLinux Images List of prebuilt Linux images that can be used with the Quick Start Guide. Free

Versal Embedded Design Tutorials (EDT)

Name Description License Type
Versal EDT Introduction to using the Xilinx Vivado Design Suite flow for a VCK190 evaluation board. The tools used are Vivado Design Suite and the Vitis™ unified software platform. Includes IP Evaluation licenses
Training & Support