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Virtual Input/Output (VIO)

Product Description

The LogiCORE™ IP Virtual Input/Output (VIO) core is a customizable core that can both monitor and drive internal FPGA signals in real time. The number and width of the input and output ports are customizable in size to interface with the FPGA design. Because the VIO core is synchronous to the design being monitored and/or driven, all design clock constraints that are applied to your design are also applied to the components inside the VIO core. Run time interaction with this core requires the use of the Vivado® logic analyzer feature.

Key Features & Benefits

  • Provides virtual LEDs and other status indicators through synchronous input ports
  • Includes optional activity detectors on input ports to detect rising and falling transitions between samples
  • Provides virtual buttons and other controls through synchronous output ports
  • Includes custom output initialization that allows you to specify the value of the VIO core outputs immediately following device configuration and start-up.
  • Run time reset of the VIO core to its initial values

Featured Documents

Tools and Device Support

Device Family Support:

Design Tools Support:

xilinx-131x43
  • Bundled With: Vivado Design Suite
  • License: Xilinx End User License Agreement

Featured Documents

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