Dynamic Function eXchange (DFX) allows designers to dynamically modify sections of the FPGA designs on-the-fly. Designers can download partial bitstreams to the FPGA while the remaining logic continues to operate. This opens a world of possibilities for real time design changes and performance enhancements. Dynamic Function eXchange can allow designers to move to fewer or smaller devices, reduce power, and upgrade systems in real-time
The Vivado™ ML Design Suite software tools unlock the capability to reconfigure a portion of a AMD FPGA or SoC while the rest of the device remains operational. The current solution leverages the impressive implementation capabilities of the Vivado ML Design Suite, reducing the overhead necessary to create reconfigurable designs. Users can implement designs using the Tcl-based non-project flow or the RTL- or IP-based project flows. IP Integrator (IPI) design support was introduced in version 2021.1 through the use of Block Design Containers. RTL and IP project modes are supported within the Vivado IDE, with many underlying flow details automatically managed. Entry points to the design flow include high level languages processed via Vitis and HLS. Advanced flow features such as Nested DFX, which enables users to subdivide a dynamic region into lower-order dynamic regions, and Abstract Shell, which streamlines the implementation tool flow, greatly improving runtime, are available in non-project mode.
Four pieces of intellectual property are available to help designers complete DFX designs more quickly and easily. The Dynamic Function eXchange Controller is a hardware-based configuration controller that can help manage all aspects of reconfiguration events, from triggering and arbitration to bitstream delivery and error handling. The Dynamic Function eXchange Decoupler can be used with the DFX Controller or with any customer controller to safely isolate the dynamic region as it is being reconfigured. The Dynamic Function eXchange AXI Shutdown Manager helps users cease activity on AXI interfaces so Reconfigurable Partitions can be safely reconfigured. The Dynamic Function eXchange Bitstream Monitor allows users to debug and monitor partial bitstreams, ensuring version and target compatibility.
Most 7 series and Zynq™ 7000 devices support Dynamic Function eXchange, with the only exceptions being the smallest devices within these families; some Artix 7 and all Spartan 7 are not supported. UltraScale™ support is complete, with all devices supported through bitstream generation in the current Vivado Design Suite version. UltraScale+™ device support covers all devices in production. Versal support was added with production status in Vivado 2021.1. See the DFX Reconfiguration User Guide (UG909), Appendix A, for the most up-to-date list.
UltraScale represented a new breakthrough in Dynamic Function eXchange technology, enabling reconfiguration of nearly all FPGA resource types, including I/O, Gigabit Transceivers, and clocking networks. UltraScale+ improved upon this capable family by streamlining bitstream delivery and expanding reconfiguration modes. Most recently, Versal support is a tremendous step forward in efficiency with software-based reconfiguration management, a reconfigurable network-on-chip, shared memory access, and floorplan granularity efficiencies.
Professors and researchers associated with universities may receive licenses for versions of Vivado software through the AMD University Program. All Vivado editions include Dynamic Function eXchange but older versions (prior to 2019) have explicit DFX license requirements. Learn more about access requirements and procedures for obtaining licenses by sending an email to email@example.com.