Expand the sections below to learn more about the new features and enhancements in Vivado™ ML 2022.2.
Infrastructure and Embedded
Storage
Gigabit Transceiver (GT) Wizard
Wired
Wireless
PCIe® Subsystems
Multimedia
Footnotes:
* Measurements are done by Vivado engineering team as of October 1st, 2022 on 48 Customer designs for Versal. Comparison is of Worst Negative Slack (WNS) on Explore Strategy vs. Intelligent Design on 2022.2 Vivado ML software tool. Actual improvement uplift for commercial systems may vary based on factors including system hardware, software and driver versions, and BIOS settings.
** Measurements are done by Vivado engineering team as of October 1st 2022 on 68 designs comparing Default vs. Incremental compile on Vivado ML software tool 2022.2. Six outlier compares in excess of 6x were discarded to provide a more representative performance average. 5% of design incrementally compiled for comparison. Actual improvement uplift for commercial systems may vary based on factors including system hardware, software and driver versions, and BIOS settings.
Expand the sections below to learn more about the new features and enhancements in Vivado™ ML 2022.1.
The following devices have been enabled both in the Enterprise Edition of Vivado ML
The following devices have been enabled both in standard and Enterprise Edition
Wired
Expand the sections below to learn more about the new features and enhancements in Vivado™ ML 2021.2.
The following devices have been enabled both in the Enterprise and Standard Editions of Vivado ML
Timing and QoR Enhancements:
Ease of Use Enhancements
Add interface adaptors report in the C synthesis reports:
Analysis & Reporting
The Function Call Graph Viewer has some new features:
A new Timeline Trace Viewer is now available after simulation. This viewer shows the runtime profile of your design and allows the user to remain in the Vitis HLS GUI.
Intelligent Design Runs (IDR)
ML-based placer directive prediction
Expand the sections below to learn more about the new features and enhancements in Vivado™ ML 2021.1
ML model Integration
New Synthesis Features
Machine Learning models in implementation
opt_design -resynth_remap
Manually retime LUTs and registers during placement with XDC properties
New Features for Versal Devices
Intelligent Design Runs:
Report QoR Suggestions (RQS) Improvements
Methodology Violations in Timing Reports
New Constraint Reporting Features
DFX for Versal
BDC for DFX
Classic SoC Boot Flow Using DFX
Versal Tandem configuration for CPM4
Abstract Shell Support for Nested DFX Designs in UltraScale+
SmartLynq+ module
ChipScopy
General | Integration | Implementation | Verification |
---|---|---|---|
Device Support | Add-on for Matlab & Simulink | Synthesis | Simulation |
Install and Licensing | IP Integrator | Implementation | Debug |
IP Enhancements | Dynamic Function eXchange |
Data Center
Video and Imaging
Wired and Wireless
Storage
General
Wizards:
General | Integration | Implementation |
---|---|---|
Install and Licensing | IP Integrator | Synthesis, Implementation and Power |
IDE Enhancements | IP Enhancements | Dynamic Function eXchange |
Data Center
Wired/Wireless
General
Video and Imaging IPs
Dynamic Function eXchange (DFX)
Implementation Design Flow
Design Analysis and Timing Closure
Power Analysis
General | Integration | Implementation | Verification |
---|---|---|---|
OS / Device Support | SysGen / Model Composer | Synthesis and Implementation | Simulation |
Install and Licensing | IP Integrator | Power | Debug |
IDE Enhancements | IP Enhancements | Dynamic Function eXchange | Programming |
The following production devices are in production:
General | Integration | Implementation | Verification |
---|---|---|---|
OS / Device Support | SysGen / Model Composer | Synthesis and Implementation | Simulation |
Licensing and Install | IP Integrator | Power | Debug |
IDE Enhancements | IP Enhancements | Partial Reconfiguration | Programming |
The following production devices are enabled in this release:
Download Vivado Design Suite 2018.3 now, with support for: