What's New in Vivado


2021.1

Vivado ML What's New by Category

Expand the sections below to learn more about the new features and enhancements in Vivado® ML 2021.1

  • Versal™ AI Core Series: - XCVC1902 and XCVC1802​
  • Versal Prime Series: - XCVM1802​
  • Virtex® UltraScale+™ HBM device: ​XCVU57P
  • Flexlm version upgraded to 11.17.2.0
    • Support 64-bit versions of Linux and Windows only​
    • Customer using floating license must upgrade licensing utilities to Flexlm 11.17.2.0​
  • Block Design Container
    • 2021.1 is the production release for block design containers.  ​
    • Enables Modular Designing for Reusability​
    • Allows Team Based Designs​
    • Enables DFX Flow in the Project Mode​
    • Ability to specify variants for simulation and synthesis ​
    • Address management for BDCs from the Top-level BD
  • Vivado Store​
    • Download boards and example designs from GitHub​
    • 3rd party board partners can contribute to these repositories asynchronously to Vivado releases
  • IP/IPI Revision Control Improvements​
    • Migration of older Vivado projects to new directory structure 
  • CIPS 3.0 ​
    • IP Re-architecture of CIPS to Hierarchical Model​
    • New Modular User Interface​
  • Vivado Text Editor – Sigasi Backend​
    • Language protocol server supporting:​
      • Autocomplete​
      • Go to Definition / Find Usages​
      • Tool-tips​
      • Indent (Range only in VHDL)​
      • Syntax Errors and Warnings as you type​
      • Code folding​
      • Semantic Highlighting
  • IPI Designer Assistance for CIPS & NoC​
    • Enables intuitive Block Automation for NoC & CIPS connectivity​
    • Allows easier creation of designs that access all available memory connected to the device or on the board, e.g. DDR and LPDDR
  • Non-Power of 2 DDR Assignment through Interconnect​
    • IPI now supports non-power-of-2 (NPOT) address assignments across Address Paths with one or more SmartConnect IP​
  • IP Packager Enhancements
    • Packager customer experience improvements​
      • Connectivity of custom interfaces in IPI / Custom IP​
      • XPM memory in the packager​
      •   Ability to tag files as SV or VHDL-2008 in the packager from package an IP from a directory​
    • Production release for packaged RTL IP as Vitis kernel​
      • Kernel specific DRCs within IP packager​
      • Ease of use ​
      • Preservation of metadata in these packaged IPs for Vitis kernel usage
  • IP Enhancements – Data Center
    • PCIe Subsystems​
      • Early access support for CPM5, PL PCIE5, and GTYP in Versal Premium​
      • CPM4 support in Versal CIPS Verification IP (VIP) for simulation​
    • Introducing the Algorithmic CAM IP​
      • EA for US+ devices​
    • AXI IIC improvement to dynamic read mode function​
    • SmartConnect support for non-power-of-two address ranges​
    • XilSEM library API release & documentation in UG643​
    • SEM IP core device support additions for US+ devices
  • IP Enhancements – Video and Imaging ​
    • Video and Image Interface IPs​
      • CSI TX subsystem adds support for YUV422 10bit​
      • DisplayPort Subsystems add support for HDCP2.2/2.3 repeater feature​
      • HDMI2.1 (controlled access) adds support for Dynamic HDR, and enhanced gaming features (VRR, FVA, QMS and ALLM)​
    • New IP: Warp Processor for digitally manipulating images ​
      • Supports Keystone distortion, Barrel and Pincushion distortions and Arbitrary distortions​
      • Scaling: 0.5x, 1x, 2x; Rotation: -90 to +90 deg​
      • Resolutions from 320x240 to 3840x2160, with multichannel support​
      • Input and Output: 8/10/12 bpc YUV, RGB
  • IP Enhancements - Wired
    • 100G Multirate Ethernet Subsystem - MRMAC ​
      • 10G/25G/40G/50G/100G Ethernet NRZ GTM ​
      • MRMAC 25G Ethernet at –1LP​
         
  • IP Enhancements – Wireless  ​
    • O-RAN  ​
      • Static/Dynamic Compression/Decompression Function in the IP core (BFP + Modulation)​
      • New interface to support LTE Section Extension Type 3 information and feed an external LTE precoding block through a single interface​
      • Support for Beam ID mapping per Slot (in addition to existing per Symbol method)​
      • Support for DL Section Type 3 messages​
      • Section Type 0 added to PDxCH BID port​
      • Max Ethernet packet size increased to 16000 bytes (Support for 9600 byte jumbo frames)​
  •  IP Enhancements – Storage
    • NVMeHA now supports Versal and VU23P devices​
    • NVMeTC now supports Versal and VU23P devices​
    • ERNIC now supports Versal​
      • Native connection to the MRMAC​
    • AES-XTS available only by special request
  • IP Enhancements XPM
    • XPM_Memory and EMG now support all URAM sizes​
    • XPM_Memory and EMG now support mixed RAM combinations​
      • Use ram_style = "mixed"​ 
    • XPM_Memory and XPM_FIFO allow disabling of assertions for broader simulation support​
      •  DISABLE_XPM_ASSERTIONS define has been added
  • IP Enhancements - GT Wizard 
    • Versal GTY Wizard Production
    • Versal GTYP Wizard available as EA
    • Versal GTM Wizard available as EA    
  • Vitis HLS  2021.1 – Production Versal Support ​
  • Versal timing calibration and new controls for DSP block native floating-point operations​
  • Flushable pipeline option with lower fanout logic (free running pipeline a.k.a. frp) ​
  • Enhanced automatic memory partitioning algorithm and new config_array_partition option​
  • New “Flow Navigator” in GUI and merged views for synthesis, analysis and debug​
  • Vitis flow “never ending” streaming kernel support for low runtime overhead​
  • Function call graph viewer with heatmap for II, latency and DSP/BRAM utilization​
  • New synthesis report section for BIND_OP and BIND_STORAGE​
  • Improved data-driven pragma handling for better consistency​
  • Vivado report and new export IP widgets to pass options to Vivado​
  • New text report after C synthesis to reflect GUI information

ML model Integration

  • Machine Learning models to predict and select optimizations​
    • 30% compilation speedup for Versal designs

New Synthesis Features

  • XPM_MEMORY supports heterogeneous RAM mapping​
    • Memory array mapped using all device resource types: UltraRAM, Block RAM, and LUTRAM​
    • Most efficient use of all resources​
    • Use parameter or generic: MEMORY_PRIMITIVE(“mixed”)​
    • Does not support WRITE_MODE = NO_CHANGE​
    • VHDL-2008: new support for the to_string() function​
    • Log report includes RTL overrides of IP generics and parameters

Machine Learning models in implementation​

  • Predict routing congestion and route delays​
  • Better correlation between placement-based estimation and actual routing à better Fmax and reduced compile times​

opt_design -resynth_remap​

  • New timing-driven logic cone resynthesis optimizations that reduce logic levels​

Manually retime LUTs and registers during placement with XDC properties ​

  • PSIP_RETIMING_BACKWARD​
  • PSIP_RETIMING_FORWARD

New Features for Versal Devices​

  • Calibrated Deskew adjusts the clock network delay taps before device startup to further minimize skew​
  • Automatic pipeline insertion improves clock speed by on paths…​
    • Between PL and NoC and between PL and AI Engines
    • Available both from the AXI Regslice IP and by using auto-pipeline properties​
    • Adds latency to pipelined paths​
  • Elastic pipelines from shift register primitives (SRLs) ​
    • pipelines are built around an SRL which holds excess pipeline stages​
    • Placer builds the ideal pipeline based on source and destination placement ​
    • Stages can be pulled out of the SRL to cover a wider distance​
    • Stages are absorbed by the SRL to shrink the pipeline for shorter distances​
    • Preserves latency on pipelined paths

Intelligent Design Runs:

  • Intelligent Design Runs (IDR) gives pushbutton access to a new, powerful automated timing closure flow ​
    • report_qor_suggestions​
    • ML strategy prediction​
    • Incremental Compile​
  • Available in Vivado projects and is launched by a right-click menu selection of an implementation run that fails timing. ​The IDR Reports dashboard details the flow progress and provides hyperlinks to the related reports.​A great option for users with timing closure difficulty​
    • QoR gain average >10%

Report QoR Suggestions (RQS) Improvements​

  • DFX-aware QoR suggestions​
    • Suggestions given only on DFX modules when static is locked​
    • No suggestions that disrupt DFX boundaries​
    • Synthesis suggestions correctly scoped to global or out-of-context runs
  • Assessment included in the interactive report_qor_suggestions (RQS) GUI report

Methodology Violations in Timing Reports​

  • Timing reports now include Report Methodology summary​
    • Draws attention to methodology violations​
    • Neglected methodology violations may cause timing failures​
  • Includes the summary of the methodology violations from the latest report_methodology run​
    • Methodology violations summary stored with design checkpoint

New Constraint Reporting Features​

  • report_constant_path: new command to identify the source of constant logic values observed on cells and pins​
    • report_constant_path <pins_or_cells_objects>​
    • report_constant_path -of_objects [get_constant_path <pins_or_cells_objects>]

 

   DFX for Versal

  • Versal DFX flows available with production status​
    • Compile DFX designs from block designs to device image creation​
    • Use Vivado IPI Block Design Containers (BDC) for creating Versal DFX designs​
  • Leverage DFX IP in Versal just as with UltraScale, UltraScale+ ​
    • DFX Decoupler IP, DFX AXI Shutdown Manager IP to isolate non-NoC interfaces​
  • All programmable logic is partially reconfigurable​
    • From NoC to clocks to hard blocks​
  • AIE full array Dynamic Function eXchange support​
    • Supported through Vitis platform flows

BDC for DFX

  • Block Design Containers (BDC) for DFX released in IP Integrator​
    • Supports all architectures, critical for Versal​
  • Place a block design within a block design to create and process DFX designs​
    • UG947 shows IPI BDC tutorials for Zynq UltraScale+ and Versal devices​
    • More DFX tutorials to be posted on GitHub

Classic SoC Boot Flow Using DFX​

  • Classic SoC Boot flow available for Versal designs​
    • Enables users to quickly boot their DDR-based processing subsystem and memory to run Linux prior to loading the programmable logic​
    • Separate programming events in Versal to emulate the Zynq boot flow​
    • Auto-Pblock generation used in this flow​
    • Not compatible with CPM

Versal Tandem configuration for CPM4

  • Tandem PROM and Tandem PCIe for CPM4 available​
  • Users who require 120ms configuration of ​a PCIe end point now have a selection in ​
    the CIPS customization GUI to select the ​Tandem Configuration mode​
    • Tandem PROM – load both stages from flash​
    • Tandem PCIe – load stage 1 from flash, ​
      stage 2 over PCIe link via DMA​
    •  None – standard boot      

Abstract Shell Support for Nested DFX Designs in UltraScale+

  •  Subdivide your Reconfigurable Partition (RP) into multiple nested RPs using Nested DFX (pr_subdivide)​
  • Create Abstract Shell for each nested RP (write_abstract_shell)​
  •  Accelerate the implementation of each Nested RP by using its Abstract Shell
  • VHDL-2008 Enhancements ​
    • Unconstrained Arrays​
    • ·Conditional Operators​
    • Unary Reduction Operators​
  • Code Coverage Support​
    • write_xsim_coverage command support for writing intermediate coverage database

SmartLynq+ module

  • Optimized for Versal High-Speed Debug Port (HSDP)​
    • Faster device programming & Memory access ​
    • High speed data upload & download​
    • Data storage: 14GB DDR memory on module​
  • High-Speed Debug Port (HSDP) Support​
    • Support for connecting to Aurora based HSDP over USB-C connector​
  • PC4 and USB based JTAG​
  • Serial UART support

ChipScopy

  • Open-Source Python API for ChipScope​
    • Control and communicate with Versal Device and Debug Cores​
    • Vivado not required to use – just need a PDI/LTX​
    • Benefits​
      • Build custom debug interfaces​
      • Interface with python ecosystem​
2020.2

Device Support

  • Versal AI Core series : XCVC1902 and XCVC1802
  • Versal Prime Series : XCVM1802
  • Zynq UltraScale+ RFSoC: XCZU43DR, XCZU46DR, XCZU47DR, XCZU48DR, XCZU49DR

Install and Licensing

  • Petalinux is now a part of the Xilinx Unified installer in addition to the existing standalone installation offering.

IP Integrator

  • Revision Control Improvements
    • New directory structure separating sources from output products
    • BD/IP output products are no longer placed in the project.srcs directory.
    • All output products reside in the project.gen directory parallel to the project.srcs.
  • Address Map Enhancements
    • Graphical view of Address Map in HTML
  • Vitis Platform Creation Improvements
    • Ability to identify Vivado Project as an extensible platform project during Project Creation and in Project Settings​
    • Add new Platform Interface validation DRCs
    • Run Platform DRCs during validation for platform BDs​
    • New Platform Setup GUI​
  • IP Caching improvements
    • Ability to create and use Read-Only zipped IP Caches ​
    • Zipped Cached can be pointed to and need not be unzipped
  • Block Design Container 
    • Instantiate a BD inside another BD​
  • CIPS (Control, Interfaces and Processing System) – Versal
    • Example Designs in XHUB stores – Versal ​

IP Enhancements

Data Center

  • Queue DMA Subsystem for PCI Express (QDMA) device support expansion
    • Gen3x8 in "-2LV" UltraScale+ devices
    • Gen4x8 in "-2LV" Virtex UltraScale+ VU23P device
  • Versal ACAP subsystems for PCI Express targeting GTY, PL PCIE4, and CPM4 integrated blocks
    • Integrated Block for PCI Express (GTY + PL PCIE4)
    • DMA and Bridge Subsystem for PCI Express (GTY + PL PCIE4 + Soft QDMA, XDMA, AXI-Bridge)
    • CPM Mode for PCI Express (GTY + CPM4)
    • CPM DMA and Bridge Mode for PCI Express (GTY + CPM4 + Hard QDMA, XDMA, AXI-Bridge)
    • PHY for PCI Express (GTY)

Video and Imaging

  • MIPI 
    • DPHY rates on Versal devices increased: 3200Mbs on -2 and -3 devices, 3000Mbs on -1 devices
    • Added YUV420 output support for CSI RX core
  • DisplayPort 1.4 Subsystems
    • YUV420 support, Adaptive sync, Static HDR
    • eDP IP option in general access 
  • SDI subsystems
    • HLG HDR support
    • Versal VCK190 pass thru example design
  • HDMI2.0 adds support for HDCP2.3

Wired and Wireless

  • JESD204C Full Production
  • New 200G RS-FEC for UltraScale+ and Versal
  • 1G/10G/25G Ethernet adds 1-step and TSN support
  • Versal MRMAC 1-step 1588 hardware timestamping​
  • 10G/25G MRMAC Ethernet 2-step 1588 linux driver support 

Storage

  • New ERNIC features
    • resource optimizations for 100G sustained bandwidth support
    • support for the new VU23P device
    • Improvements to Priority Flow Control (PFC)
  • NVMeTC now supports the new VU23P device
  • Lossless Compression IP, GZIP and ZLIB algorithms
  • NVMeOF Reference Design now available for both Alveo U50 and Bittware 250-SoC boards

General

  • XPMs
    • XPM_CDC is now available through IPI
    • URAM Initialization Support for Versal
  • Infrastructure and Embedded
    • New SmartConnect features
      • Priority arbitration
      • Low area mode
  • EMG (Embedded Memory Generator) in IPI for Versal, replacing Block Memory Generator
  • EFG (Embedded FIFO Generator) in IPI for Versal, replacing FIFO Generator

Wizards:

  • Wizards now available for Versal
    • GTY Transceivers Wizard
    • Advanced IO Wizard
    • Clocking Wizard
  • New Transceiver Wizard features
    • Full Block Automation, with lane selection
    • On-the-fly reconfiguration (Versal only)
    • Quad sharing (Versal only)
    • Transceiver Bridge IP (Versal only)
  • High level Synthesis
    • Vitis HLS replaces Vivado HLS in Vivado (was already default for Vitis in v2020.1)
    • Adds array reshape and partitioning directives for top ports
    • Simplified toolbar icon layout with new reporting sections for interfaces and AXI-4 bursts
    • Inference for single clock cycle floating point accumulation in DSP blocks for Versal
    • Tcl files can create a project and open it in the GUI directly (vitis_hls -p  <file>.tcl)
    • New single click filter for non-default options in “Solution Settings”→”General”
    • Constrained random testing for AXI interfaces now visible in the GUI
    • On-chip block RAM ECC flags option via the bind_storage pragma
    • Interactive FIFO depth sizing in GUI during CoSim
    • Support for SIMD programming (vector data types)

Add-on for Matlab & Simulink:

  • Unified installer will give them both Model Composer and System Generator in one launcher

Simulation

  • VHDL-2008 support
    • Shift Operators (rol, ror, sll, srl, sla and sra)
    • Mixing Array and Scalar Logical Operators
    • Conditional Sequential Assignments on signal
    • Case Generate
    • Extensions to Globally Static and Locally Static Expressions
    • Static Ranges and Integer Expressions in Range Bounds
  • Support for cross language Hierarchical name
    • Verilog hierarchical name will be enabled to access VHDL signals from SV/Verilog modules 
  • Simulator support for Versal
    • Xilinx Simulator
    • 3rd party Simulators
      • Cadence Xcelium 
      • Mentor Graphics Questasim

Hardware Debug

  • Versal AXIS-ILA
  • Debug flow improvements
  • Debug block automation improvements
  • Support for selecting URAM and AXIS-ILA trace storage 

Synthesis

  • Support for System Verilog string type
  • Fixed and floating-point package support in VHDL-2008
  • Automatic pipelining for heterogeneous RAMs
  • Logic Compaction directive is extended to Versal LOOKAHEADs

Implementation Design Flow

  • Placer replication (PSIP) improvements
  • Power rail definition and power analysis
  • BUFG-to-MBUFG global buffer conversion (Versal)

Design Analysis and Timing Closure

  • RQA and RQS improvements

Dynamic Function eXchange (DFX) 

  • Abstract Shell for Dynamic Function eXchange
  • Isolation design flow(IDF) + DFX in one design 
2020.1

Install and Licensing 

  • Download Verification(Digest and Signature) support for Windows
  • Download only feature for Web installer now supports two options 
    • Download full image (All Products)
    • Download selected products only (smaller size)

IDE Enhancements

  • New example design and board file download utility.  Download only what you need and gain access to vast library of Xilinx and 3rd Party solutions on github.
  • New and improved example designs available by download 

IP Integrator

  • Introducing new “Path” and “Network” concepts
    • Maintains familiar look and feel
  • Full cross-probing with Address Editor
    • Highlight by paths and/or networks
  • Realtime error highlighting
    • Tooltip provides failure details
  •  New “Address Path” panel
    • Verbose path details
  • New “Addressing View” emotional view
    • Simplified for Addressable content only
    • Clean view of Addressing connectivity

IP Enhancements

Data Center

  • ERNIC IP Enhancements
    • Bandwidth and latency have been improved to operate at 100GE line rates.
    • Enhanced to support 64-bit address. New functions are now available: PFC function and Immediate Command.
  • New AES IP, for Data Center encryption applications.
  • New NVMe Target Controller IP joins the Host Accelerator for storage acceleration.
  • NVMeOF turnkey U50 Alveo solution is now available. Includes an FPGA bitfile and documentation.
  • Major revision to Queue DMA Subsystem for PCI Express (QDMA 4.0) to improve timing, reduce resource utilization, and simplify forward migration.

Wired/Wireless

  • Wireless
    • JESD204C support added for GTH3/4 – Preproduction 2020.1
    • New ORAN Radio Interface IP which provides O-RU (O-RAN radio unit) function with dedicated SRS/PRACH AXI-stream and 32 spatial streams.
    • New 400G FEC IP soft and optional implementation that leverages US+ 58G GTM hard 50G KP4 FEC to save area and power.
  • Wired
    • AXI Ethernet added support for switchable SGMII and 1000BASE-X
    • 50G Ethernet Subsystem added optional soft 50G 'KP2' NRZ FEC
    • Integrated 100G Ethernet Subsystem added optional soft 100G 'KP4' NRZ FEC

General

  • Firewall IP - protects either the upstream or downstream directions. This IP helps isolate regions in FPGA-as-a-Service and other applications.
  • SmartConnect IP optimized for lower area modes, also 1x1 coupling and converting functions.

Video and Imaging IPs

  • SDI Subsystems adds 12bpc and HFR in native video interface mode
  • MIPI CSI Transmit subsystem adds support for raw16 and raw20 color formats
  • Video mixer adds options to select colorimetry  BT.709 and BT.601 Support
  • HDMI2.0 Subsystems add 32 channel audio and 3D audio support

Synthesis

  • Ability to override HDL attributes using XDC constraints enables modifying synthesis behavior without modifying HDL source code.
  • Reuse and integrate designs from different languages with enhanced generic- and parameter-passing between different languages in the same design.
  • Tool performance is significantly improved when handling function calls. Improvements were made for all languages.
  • A new directive called Logic Compaction implements lower-precision arithmetic functions using minimal logic resources.
  • Memory mapping is significantly improved by balancing arrays over different resource types to avoid high utilization of a particular resource type.

Implementation

Dynamic Function eXchange (DFX)​

  • Nested DFX allows users to place one or more dynamic regions within a dynamic region to further extend the flexibility of DFX
    • Supports UltraScale and UltraScale+ 
    • Production status, no project support 
  • Benefits
    • Simpler verification
    • Data Center card uptime
    • Finer granularity
  • All existing IP for Partial Reconfiguration have been superseded by equivalent IP with Dynamic Function eXchange terminology 
    • IP are functionally equivalent to their predecessors and are easily upgraded from PR to DFX

Implementation Design Flow

  • Pblocks are now SOFT type by default
  • The only exception: DFX Pblocks have hard boundaries by definition and cannot become SOFT
  • Benefit
    • Cell placement outside Pblock boundaries can improve design performance(shorter wirelength, less congestion) 

Design Analysis and Timing Closure​

  • Report QoR Suggestions predicts up to 3 custom strategies for better performance 
    • Predicted to give better results than Default and Performance_Explore
    • Saves compile time and effort to sweep many strategies. 
    • Run report_qor_assessment (RQA) to check if the design is compatible with strategy prediction.
  • report_ram_utilization report has been completely overhauled to provide relevant information.
    • Make memory resource trade offs
    • Identify Inefficient DRAMs
    • See post opt optimizations
    • Performance / Power Bottlenecks

Power Analysis

  • Vivado now supports reporting by power rail
    • Power reports calculate total current vs. current budgets for both rails and supplies
    • Power rail definitions are included in board files
  • Rail reporting now available for Alveo U50 
2019.2

Device Support

The following production devices are in production:

  • Virtex UltraScale+ HBM:- XCVU31P, XCVU33P, XCVU35P, XCVU37P

Install and Licensing 

  • Introducing Xilinx Unified installer ​for an easier install of all Xilinx tools. The single unified installer enables users to install all Xilinx tools such as Vitis​, Vivado​, On-premise Install for Cloud Deployments​, Bootgen​, Lab Edition, Hardware Server and Document Navigator.

IDE Enhancements

  • Next gen linter in text editor (Sigasi based)​
    • Improved syntax checking​
    • Autocompletion​
    • Go to definition​
    • Find usages​
    • Auto formatting / indenting​
    • Enabled by project settings​

Model Composer

  • Improved Support for Vector Signal Dimensions: Improvements to code generation infrastructure to handle vector [N] signals in the design, resulting in improved performance
  • Constant Block Enhanced for Vector Parameters: Constant block now supports interpreting vectors parameters as 1-D, similar to corresponding Constant block in Simulink library
  • New Example Designs with Optimized DSP Blocks
    • MRI Image Reconstruction with 2D-FFT
    • Low-pass Filter design using FIR Block
    • Image Smoothing filter using FIR Block
  • Enhancements to C/C++ Function Import: Improved error and warning messages displayed in Diagnostic Viewer, enabling better troubleshooting of issues with custom code.
  • Customize IP Properties for IP Catalog Export Type: Specify IP Properties including name, version and hardware description language (VHDL or Verilog) for the IP packaged from the synthesized design.
  • Search Capabilities in Device Chooser: Quickly search for parts and boards, based on multiple criteria, using the Device Chooser dialog on the Model Composer Hub block.
  • FIR Block Supports Multi-Channel Processing: Enhancements to the FIR block support processing columns in the incoming signal as independent channels of data for multi-channel filtering operations.
  • Supported MATLAB Versions: R2018a, R2018b, R2019a and R2019b

IP Integrator

  • Versal support and block automation for GT wizard with IPs.  Allows for mixing IP protocols in a GT Quad.
  • Hide or color nets / blocks for better visibility in the block diagram​

IP Enhancements

  • SmartConnect Enhancements​
    • New area optimization for smaller switch configurations
    • LinkBlaze Topology support​
    • SystemC model​ now available
  • URAM Readback/Writeback IP for UltraScale+ Devices​
    • Solves the problem of accessing URAM data for debug​
    • Allows data initialization​
  • HBICAP
    • Enables embedded processors to access FPGA configuration memory through the Internal Configuration Access Port (ICAPEx)
    • Gives users the ability to modify circuit functionality during operation
  • FIR Compiler
    • Versal optimization to DSP58 new features and wider bus widths
  • Discrete Fourier Transform (DFT)
    • Enhancements for 5G
    • Support all point sizes to satisfy 38.211
    • Async release to 2019.2 (EA only)
  • LTE Downlink Channel Encoder
    • Bug fix: issue with incorrect behaviour if tvalid input de-asserted on a particular cycle resolved
  • Video and Imaging IPs
    • MIPI DSI TX: Add 2.5Gb/s DPHY and DCS long packet support
    • MIPI CSI RX: new resources optimization option by removing register interface. 
    • Spartan 701 MIPI CSI RX to DSI TX based application example design
    • DisplayPort Subsystems: HDCP2.2 example design
    • SDI Subsystems add YUV 444 support 

RTL Synthesis

  • SystemVerilog Virtual Interface support​
  • VHDL language support enhancements​
    • Support for the TIME physical type​
    • Faster compile times for functions​
    • Improved error handling​
  • XPM_MEMORY​
    • Asynchronous resets on output registers of asymmetric RAMs​
    • Supported for both Block RAM and UltraRAM​
  • Allow optimization of instances with MARK_DEBUG pins​
    • Previously treated as DONT_TOUCH​
  • Retiming control sets of register pipelines to enable mapping to SRLs​

Implementation

  • Dynamic Function eXchange (DFX)​
    • Partial Reconfiguration (PR) is part of the overall DFX solution​
      • DFX includes silicon capabilities, Vivado design flows, Partial Reconfiguration IP and more​
      • Across all architectures, from 7 series through Versal​
      • New features to aid designers coming in future releases​
      • Read more on Xilinx.com​​
    • AXI High-Bandwidth ICAP interface IP​
      • Supports AXI read and write bursts of 256 beats per transaction​
      • Optional AXI4-Stream master interface for read datapath with unlimited burst per transaction​
      • Memory mapped AXI4 slave interface​
      • Supports write and read transfers up to 230 bytes in size​
      • Documented in PG349 ​
  • Implementation Design Flow
    • PhysOpt is now enabled by default in Vivado Implementation Defaults strategy​
    • New phys_opt Default directive​
      • Fewer optimized paths than prior releases​
      • Focuses on addressing timing outliers​
      • Very quick runtime​
    • LUT combining optimization added to "Physical-Synthesis-in-Placer" (PSIP)​
    • New optimization for BUFG/CE path in opt_design​
      • Reduces clock skew for timing closure
  • Design Analysis and Timing Closure​
    • RQS Strategy Prediction​
      • Uses ML to predict top 3 Implementation Strategies​
      • report_qor_suggestions -strategy
    • RQA (report_qor_assessment)​
      • Provides guidance for using incremental compile and RQS implementation strategies​
      • Adds report_failfast summary to catch design issues before implementation​
    • New congestion metric: interconnect congestion level for improved congestion visualization (Windows -> Metrics)​
    • report_ram_utilization addition of LUTRAM reporting​
    • New UltraFast methodologies to check for unsafe CDC between MMCMs
  • Incremental Compile​
    • Incremental Implementation directives​
      • Quick: fastest runtime with minimal timing effort
      • RuntimeOptimized: fast runtime while maintaining timing​
      • TimingClosure: tries to meet timing​
      • No need to modify place and route directives​
        • Tools automatically decide to run Incremental or default with original directives​
    • Improved phys_opt_design performance in Incremental Implementation flow​
      • More pinpointed optimization​
      • Overall better P&R reuse​
    • Incremental Synthesis: design reuse now considers changes to synth_design options​

Vivado Simulator

Simulation

  • Introducing UVM 1.2 support in Vivado Simulator(XSIM)​ to enable users to create high quality verification environment​ using UVM-based testbenches

 

2019.1

Device Support

The following production devices are enabled in this release:

  • Space-Grade Kintex UltraScale:- XQRKU060
  • XA Kintex-7:- XA7K160T
  • Virtex UltraScale+ HBM (-3):- XCVU31P, XCVU33P, XCVU35P, XCVU37P

Vivado Tools

  • General

    • Support for command-line based Web Installer has been added that enhances user experience and productivity for installing Xilinx tools
    • Disk usage optimization enabled to reduce install footprint of Vivado tool
    • Xilinx has discontinued offering DVDs for Vivado tool

  • System Generator for DSP

    • 2 New Super-Sample Rate (SSR) Blocks:Vector Assert and Vector Relational blocks added to the Xilinx SSR Block Library for building Super-Sample Rate (SSR) Designs for Xilinx devices, including the Zynq UltraScale+ RFSoC parts. Please refer to the User Guide for more information on Super-Sample Rate designs and the new block library.
    • Supported MATLAB Versions:R2018a, R2018b and R2019

  • Vivado High Level Synthesis

    • C functions can be tagged as black-boxes, replaced by equivalent RTL modules supplied by the user
    • The scope of dataflow applicability can now be extended to support multiple readers of an array through the new “stable” pragma/directive
    • A sequence of dataflow ping-pong buffers can be specified through the stream pragma/directive to improve parallel execution
    • Modified resource pragma/directive for memory allows to specify storage type and latency
    • User can set ap_ctrl_none scoped to a dataflow region to improve throughput
    • C libraries
      • C++ templated super sample rate (SSR) FFT function. Systolic architecture supporting multiple data samples (integer or fixed point) at each clock cycle
      • Enhanced OpenCV support through xfOpenCV (release notes)
      • The full set of math.h functions is now natively optimized for fixed point data types

  • RTL Synthesis

    • Added VHDL-2008 features including generics in packages, generic types in entities, and functions in generics.
    • Incremental Synthesis now available, with optional auto-incremental mode for Vivado projects.

  • Model Composer

    • DSP Block Library: New FFT, IFFT and FIR blocks are now available to design and implement signal processing algorithms with Model Composer
    • Enhancements to Throughput Control: Expanded list of blocks supported for Throughput Control. Build designs with supported blocks and control the throughput requirements of the implementation without making any structural changes to the design
    • Additional Blocks that Support Streaming Data: Design and Implement algorithms with high-throughput requirements using an expanded set of blocks that support operations on streaming data. Examples: Look-up Table, Delay, Matrix Multiply, Submatrix etc.
    • Enhanced Complex Support in C/C++ Function Import: Added support for importing functions that use hls::x_complex types as well, in addition to std::complex, expanding the support for complex signals in custom blocks.
    • Enhancements to C/C++ Function Import: Create custom "Source" blocks for your design using the xmcImportFunction feature
    • Improved Support for Row-Matrix and Column-Matrix Signal Dimensions: Improvements to the code generation infrastructure to handle Row-Matrix [Nx1] and Column-Matrix [1xN] signals in the design, resulting in improved performance.
    • Supported MATLAB Versions: R2018a, R2018b and R2019a

  • Interactive Design Environment

    • Automatically add new runs to the project summary dashboards
    • Ability to'Save As' for report strategies

  • Board Flows and Example Designs

    • Download and install third party boards directly from Github with a single click in the GUI
       
  • Vivado Simulator

    • Introducing support for SystemVerilog functional coverage and report generation(.txt or .html)
    • Support for assertion on property and sequence in concurrent region
    • Enhanced constraint randomization supportNew protocol instance window to display AXI interfaces in design
    • “Mark Simulation” feature in block diagram to add AXI interfaces in waveform viewer directly
       
  • IP Security

    • Encrypted blocks in the design will be hidden in Schematic and Hierarchy viewer. New right xilinx_schematic_visibility has been introduced that can be toggled on/off to change the default behavior
    • Updated Xilinx Vivado public key as a part of regular security update
       
  • Implementation

    • New AXI Regslice IPs to cross SLRs at high speed and automatically insert pipelines.
      • Improves Virtex UltraScale+ HBM design performance (up to 450 MHz).
      • Enabled for all UltraScale and UltraScale+ devices.
      • Property-based mechanism available for custom busses and interfaces.
    • Faster physical optimization of high-fanout nets during placement.
    • Automatic SLR crossing register usage is enabled to boost performance and reduce QoR variation
    • Report Methodology runs up to 2 times faster for designs with many timing exceptions.
    • opt_design adds an SRL remap option to convert between SRL shift register primitives and register chains. Allows balancing utilization and performance.

  • Constraints and Analysis

    • Soft Pblocks: Pblock boundaries can be made soft to allow cells to move as needed to improve performance.
    • SLR Pblocks: Pblock ranges can now be specified using SLRs for much simpler definition.
    • The report_methodology command adds new timing-related methodology checks.
    • Suggestions from report_qor_suggestions (RQS) are now object-based and are automatically applied by implementation flow commands.
    • The report_ram_utilization command is rebuilt to provide more meaningful statistics on sparseness and timing criticality.

  • Power Analysis

    • UltraScale+ XPE includes more detailed RF Data Converter settings for power analysis of Zynq UltraScale+ RFSoC Gen 3 devices.
    • UltraScale+ XPE adds an HBM wizard for system-level parameter entry for HBM power analysis, automatically generating the corresponding spreadsheet entries.

  • Vivado Debug

    • IBERT GTM: GTM transceivers line rates of 9.8 Gb/s up to 58 Gb/s using PAM4 and NRZ modulations are now supported in IBERT design for GTM and Serial I/O Analyzer. Forward Error Correction (FEC) mode with PAM4 signaling is provided in 160-bit data width mode and internal PRBS patterns (no FEC support for NRZ). In addition,new plotting features are offered for eye slicers, histograms, and signal-to-noise ratio information of different links.
    • Busplot Viewer: Logic Analyzer now offers the Busplot Viewer capability for debugging DSP & RF applications. This allows users to plot different graphs based on the probe values vs. time or samples as well as other probes data. The Viewer lets user to select any signal to use as data for X and Y axis as well as plotting multiple graphs on the same plot.
    • HBM Monitor: New memory debug capability for monitoring HBM design status and performance. Similar to memory calibration debug, the HBM Monitor dashboard will show calibration status and static temperature of HBM memory modules along with various throughput information and monitor activity on different channels.
    • RF Analyzer: The RF Analyzer tool for debugging ZU+ RFSoC devices is now available. The tool is primarily used on user boards to help understand the performance of the board in high frequency applications. The RF Analyzer uses the same basic GUI as the RFSoC Evaluation Tool. While offering many similar features, RF Analyzer is board-independent. Without using specific board implementations information, RF Analyzer relies on BRAM buffers instead ofDDR RAM, requires users to configure an external PLL if the board requires so, and communicates via JTAG between the host PC and the target board.
  • Intellectual Property (IP)

    • New 50G RS-FEC (544,514): New FEC (2x26G) NRZ used for 5G wireless applications to enable PAM-4 applications when adding an external bitmux chip
    • IntegratedUltraScale/UltraScale+ 100G Ethernet Subsystem: New optional AXI data bus interface allowing standard based interface
    • 10G/25G Ethernet Subsystem, 40G/50G Ethernet Subsystem, IntegratedUltraScale/UltraScale+100G Ethernet Subsystem, USXGMII, 1G/10G/25G Ethernet Switching Subsystem: Size optimized statistic counter by creating statistics logic based on features selected
    • Video and Imaging IPs: Video processing cores add support for 8K30 resolutions; Video mixer adds 16 layer mixing; Framebuffers adds support for 12 and 16bpc;
    • SmartConnect: Improved area efficiency, especially for small configurations and AXILite endpoints
    • AXI Bram Controller: Improved performance for single beat transactions. Configurable read latency for tight timing margins.
  • Partial Reconfiguration

    • Licenses for Partial Reconfiguration are no longer required for any Vivado Edition

2018.3

Download Vivado Design Suite 2018.3 now, with support for:

  • Virtex UltraScale+ 58G ES1 devices:- XCVU27P, XCVU29P
  • Virtex UltraScale+ HBM: XCVU31P, XCVU33P, XCVU35P, XCVU37P

  • Vivado Features:
    • QoR Improvements - 3% higher Fmax and 2x faster router compile times than 2018.1 (UltraScale+)
    • Easily compare report results across runs or run steps
    • New AXI-transaction based waveform viewer
    • Diff block diagrams for easier version control
    • Early timing closure analysis with Report QoR Analysis
              
  • IP Subsystems/Cores:
    • Wireless: New 10G and 25G Radio over Ethernet Framer 
      • eCPRI Example Design
      • NGFI IEEE 1914.3 support
    • Wireless: New 25G Time Sensitive Networking (TSN) for 802.1CM
    • Wired: 400G200G100G and 50G Ethernet support for US+ 58G GTMs
    • HBM analysis cockpit available through HW debugger
    • Video IP: All HLS Video Processing cores are now license free and come installed with Vivado (VPSS, Video Mixer, Video TPG, Frame Buffer WR/RD, Gamma LUT, Demosaic, VTC.  Two new cores for Scene Change detection and Multi output scaler
       
  • Embedded Software:
    • PetaLinux switch to standalone XSCT infrastructure
    • More robust multimedia infrastructure, including audio support
    • New license removes device restriction
    • Xen Hypervisor upgraded to Xen 4.11
    • Support for 64-bit memory addressing in MicroBlaze
  • Production Devices:
    • Defense-Grade Zynq UltraScale+ RFSoC:- XQZU21DR (-1M), XQZU28DR (-1M, -1, -1LV, -1L, -2)
    • Defense-Grade Zynq UltraScale+ MPSoCs:- XQZU3EG( -1M, -1, -1LV, -1L, -2), XQZU9EG ( -1M, -1, -1LV, -1L, -2)