Install and Licensing
- Download Verification(Digest and Signature) support for Windows
- Download only feature for Web installer now supports two options
- Download full image (All Products)
- Download selected products only (smaller size)
- New example design and board file download utility. Download only what you need and gain access to vast library of Xilinx and 3rd Party solutions on github.
- New and improved example designs available by download
- Introducing new “Path” and “Network” concepts
- Maintains familiar look and feel
- Full cross-probing with Address Editor
- Highlight by paths and/or networks
- Realtime error highlighting
- Tooltip provides failure details
- New “Address Path” panel
- New “Addressing View” emotional view
- Simplified for Addressable content only
- Clean view of Addressing connectivity
- ERNIC IP Enhancements
- Bandwidth and latency have been improved to operate at 100GE line rates.
- Enhanced to support 64-bit address. New functions are now available: PFC function and Immediate Command.
- New AES IP, for Data Center encryption applications.
- New NVMe Target Controller IP joins the Host Accelerator for storage acceleration.
- NVMeOF turnkey U50 Alveo solution is now available. Includes an FPGA bitfile and documentation.
- Major revision to Queue DMA Subsystem for PCI Express (QDMA 4.0) to improve timing, reduce resource utilization, and simplify forward migration.
- JESD204C support added for GTH3/4 – Preproduction 2020.1
- New ORAN Radio Interface IP which provides O-RU (O-RAN radio unit) function with dedicated SRS/PRACH AXI-stream and 32 spatial streams.
- New 400G FEC IP soft and optional implementation that leverages US+ 58G GTM hard 50G KP4 FEC to save area and power.
- AXI Ethernet added support for switchable SGMII and 1000BASE-X
- 50G Ethernet Subsystem added optional soft 50G 'KP2' NRZ FEC
- Integrated 100G Ethernet Subsystem added optional soft 100G 'KP4' NRZ FEC
- Firewall IP - protects either the upstream or downstream directions. This IP helps isolate regions in FPGA-as-a-Service and other applications.
- SmartConnect IP optimized for lower area modes, also 1x1 coupling and converting functions.
Video and Imaging IPs
- SDI Subsystems adds 12bpc and HFR in native video interface mode
- MIPI CSI Transmit subsystem adds support for raw16 and raw20 color formats
- Video mixer adds options to select colorimetry BT.709 and BT.601 Support
- HDMI2.0 Subsystems add 32 channel audio and 3D audio support
- Ability to override HDL attributes using XDC constraints enables modifying synthesis behavior without modifying HDL source code.
- Reuse and integrate designs from different languages with enhanced generic- and parameter-passing between different languages in the same design.
- Tool performance is significantly improved when handling function calls. Improvements were made for all languages.
- A new directive called Logic Compaction implements lower-precision arithmetic functions using minimal logic resources.
- Memory mapping is significantly improved by balancing arrays over different resource types to avoid high utilization of a particular resource type.
Dynamic Function eXchange (DFX)
- Nested DFX allows users to place one or more dynamic regions within a dynamic region to further extend the flexibility of DFX
- Supports UltraScale and UltraScale+
- Production status, no project support
- Simpler verification
- Data Center card uptime
- Finer granularity
- All existing IP for Partial Reconfiguration have been superseded by equivalent IP with Dynamic Function eXchange terminology
- IP are functionally equivalent to their predecessors and are easily upgraded from PR to DFX
Implementation Design Flow
- Pblocks are now SOFT type by default
- The only exception: DFX Pblocks have hard boundaries by definition and cannot become SOFT
- Cell placement outside Pblock boundaries can improve design performance(shorter wirelength, less congestion)
Design Analysis and Timing Closure
- Report QoR Suggestions predicts up to 3 custom strategies for better performance
- Predicted to give better results than Default and Performance_Explore
- Saves compile time and effort to sweep many strategies.
- Run report_qor_assessment (RQA) to check if the design is compatible with strategy prediction.
- report_ram_utilization report has been completely overhauled to provide relevant information.
- Make memory resource trade offs
- Identify Inefficient DRAMs
- See post opt optimizations
- Performance / Power Bottlenecks
- Vivado now supports reporting by power rail
- Power reports calculate total current vs. current budgets for both rails and supplies
- Power rail definitions are included in board files
- Rail reporting now available for Alveo U50