Here's a quick overview of Vivado® ML features for Implementation. Click the other tabs for complete feature details.
Vivado implementation is the placement and routing tool for Xilinx® devices, generating bitstreams and device images from a synthesized netlist. Implementation enables creation of platforms and custom designs of all sizes from the smallest MPSoCs to the largest monolithic and Stacked Silicon Interconnect Technology (SSIT) devices containing millions of logic cells. Vivado implementation is built on state-of-art partitioning, placement, and routing algorithms guided by Machine Learning-based predictors. Application of ML models allows implementation to achieve higher Quality-of-Results (QoR) in a shorter amount of time with an accurate prediction of routing delays and congestion. Implementation is driven by Xilinx Design Constraints (XDC) to meet design goals for performance, utilization, and power and synthesis works within Vivado Projects and Tcl scripting.
Implementation supports all modes of operation from the pushbutton mode for ease-of-use to sophisticated customized Tcl recipes for handling designs with the toughest performance requirements. Detailed analysis of timing, utilization, power, and other design quality metrics can be performed at any compilation stage: pre-placement, post-placement, and post-routing. The design database can also be saved and restored at any compilation stage using design checkpoint (DCP) files and the design can be visualized and constrained accordingly.
Implementation consists of the following processes:
A design can be analyzed at any compilation stage within implementation. At the center of analysis capabilities are:
Vivado implementation supports all levels of customization from pushbutton operation to exploration of different compilation strategies and iterative flows for designs with difficult-to-meet requirements.
Vivado logic synthesis is a design creation tool enabling hardware designers to produce optimal platforms, IP, and custom designs targeting all the latest Xilinx devices. Logic synthesis translates Register Transfer Level (RTL) designs written in SystemVerilog, VHDL, and Verilog into a synthesized netlist of library cells for downstream Implementation. Being aware of the target technology, synthesis can infer functions from RTL descriptions that map directly to dedicated silicon structures including LUTRAMs, Block RAMs, shift registers, adder-subtractors, and DSP blocks. Synthesis results are driven using attributes, tool options, and Xilinx Design Constraints (XDC) to meet design goals. Logic synthesis works within Vivado Projects and Tcl scripting and provides a solid foundation for other high-level design methods that generate RTL descriptions including High-Level Synthesis and IP integrator.
Logic synthesis has introduced Machine Learning to help speed up compilation. ML models improve overall efficiency by predicting the synthesis optimizations needed for different parts of the design.
Logic synthesis supports the latest synthesizable constructs consistent with industry standards:
HDL descriptions can be visually reviewed using an elaborated design schematic that cross-probes to the related HDL source code.
Logic synthesis provides control over all aspects of inference and optimization. Assignments can be made:
Types of control include:
Vivado logic synthesis supports all levels of customization from pushbutton operation to exploration of different compilation strategies.
When used with Vivado, the UltraFast methodology helps define proper constraints, helps to properly drive the tools and analyze results, and improves overall productivity. The UltraFast Design Methodology is a collection of best hardware design practices accumulated from many years of experience of Vivado experts and their design closure successes on customer designs that push the limits of the tools and technology.
UltraFast is documented extensively in User Guides including:
To facilitate compliance with the UltraFast Methodology guidelines, UltraFast Methodology Reports are built into Vivado and generated by default for Vivado projects, providing the benefits of UltraFast without reading a single line of documentation. The Report Methodology feature generates a list of methodology violations found in the current design, broken down by category and severity level for interactive review. Reviewing and addressing the methodology violations ensures designs are given the optimal starting point for implementation, giving the highest chances for successful design closure in the shortest amount of time. Violations that are deemed acceptable can be waived so that they do not reappear in reports.
Providing constraints that are complete and correct is an important part of the UltraFast Methodology. The Timing Constraints Wizard (TCW) analyzes timing constraints and provides step-by-step guidance on supplying missing constraints and fixing invalid constraints. Constraint completeness reduces the chances of hardware bugs resulting from unconstrained timing paths while invalid constraints can misdirect compilation effort toward false timing criticality.
Power constraint quality is critical for accurate power analysis. The Power Constraints Advisor analyzes design switching activity, pinpoints areas that appear to be improperly specified, and generates turnkey XDC power constraints for proper analysis. Vivado power reports also include a confidence level indicating a low, medium, or high quality of power constraint specification, giving feedback on power constraint completeness. A high confidence level ensures the most accurate power analysis, closely matching hardware measurements.
Complementing the UltraFast Methodology for Vivado is a unique approach to automating timing closure. In addition to best practices, Vivado experts have amassed a stockpile of solutions from the successful closure of the most challenging designs. These solutions tend to be procedural as described in the UltraFast Methodology timing closure references. Automated timing closure in Vivado goes a step further and performs these steps in response to specific timing failures, then generates turnkey solutions for each specific problem. These solutions benefit hardware designers at all levels of expertise by eliminating the lengthy manual process of reviewing tool reports, crafting possible solutions, and compiling each solution to review results and potentially iterate countless times to close timing.
The Report QoR Assessment (RQA) feature predicts a design's likelihood of meeting timing goals. It reports a simple score from 1 to 5 that indicates the degree of likelihood, 1 being least likely and 5 being most likely. In addition to an assessment score, RQA indicates the types of issues responsible for the score, the summary of methodology violations, and suggested next steps for improving a low assessment score. When run early in the compilation process, RQA helps determine whether to proceed with compilation or avoid wasted effort when chances of compilation success are minuscule.
The Report QoR Suggestion (RQS) feature is the foundation of timing closure automation in Vivado. At the center of RQS is an analysis engine that generates suggestions for fixing the top critical paths in the current compilation run. A suggestion is an object type unique to Vivado that controls how to compile the design differently to avoid the original timing closure issues. These suggestions are applied to a subsequent compilation run and Vivado follows each suggestion at the appropriate compilation stage with no required intervention. RQS is a valuable feature for iterating on a compilation run to close timing with minimal effort and supports both project and non-project modes.
Exploration has been a common practice for designs with difficult-to-meet timing requirements where many compilation strategies are run in parallel. In some cases the number of strategies can approach 20 or more which significantly lengthens design iterations and becomes a burden on computing resources. Vivado has introduced Machine Learning to predict the top three compilation strategies that are most likely to outperform all others. The ML models used to predict the best strategies can choose from dozens of custom strategies and command options, not limited to the Vivado strategy presets. By focusing on at most three strategies, the solution space is greatly narrowed and the computing resource burden is greatly reduced, resulting in much faster design iterations.
ML strategy predictions are generated by the Report QoR Suggestions feature.
Intelligent Design Runs (IDR) uses RQA, RQS, and ML Strategy Prediction as building blocks to create an aggressive, systematic timing closure process for designs with the most difficult-to-meet timing requirements. IDR runs in multiple phases:
IDR is built into the Vivado project flow as a specialized set of design runs, providing pushbutton access to a very powerful timing closure option.