Block Memory Generator


Product Description

AMD provides a flexible Block Memory Generator core to create compact, high-performance memories running at up to 450 MHz

The Block Memory Generator LogiCORE™ IP core automates the creation of resource and power optimized block memories for AMD FPGAs. Available through the (add ref to Vivado™) ISE™ Design Suite CORE Generator™ System, the core enables users to create block memory functions to suit a variety of requirements. Built-in knowledge about AMD device architectures allow it to leverage specialized FPGA architectural features to create the most compact, high performance or low power solution.

A Migration Kit is available to automate the migration to latest version of the core.

Key Features and Benefits

  • Choice of Native Interface, AXI, or AXI4-Lite
  • Example Design helps you get up and running quickly
  • Native interface core
    • Generates Single-Port RAM, Simple Dual-Port RAM, True Dual-Port RAM, Single-Port ROM, or Dual-Port ROM
    • Performance up to 450 MHz
    • Data widths from 1 to 4096 bits
    • Memory depths from 2 to 128k
    • Variable Read-to-Write aspect ratios in Virtex®-7, Kintex®-7, Virtex-6, Virtex-5 and Virtex-4 FPGAs
    • Option to optimize for resource or power
    • Ability to initialize the memories with pre-defined values
    • Supports individual Write enable per byte in UltraScale™, UltraScale+™, Zynq™ 7000, Spartan™ 7, Arti™ 7, Kintex™ 7, and Virtex™ 7 devices with or without parity
  • Native interface core (Cont.)
    • Selectable per-port operating mode: WRITE_FIRST, READ_FIRST or NO_CHANGE
    • Support for hard and soft Error Correction (ECC) feature
  • AXI interface core
    • Generates Dual Port RAM
    • Performance up to 300 MHz
    • Data widths ranging from 8 to 64 bits
  • Common features in Native interface and AXI cores
    • Variable port aspect rations for dual-port configurations
    • VHDL and Verilog behavioral models optimized for fast simulation times
    • Structural simulation model option for precise simulation

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