AMD Kintex UltraScale FPGA KCU1250 Characterization Kit
by: AMD
The KCU1250 Characterization Kit provides everything you need to evaluate the 20 GTH 16.3Gbps transceivers available on the UltraScale™ XCKU040-FFVA1156 FPGA.
Overview
Important Notice:
This development kit has been discontinued per PDN advisory XCN21011 and is no longer offered for sale. The solutions targeted for this product will not be updated moving forward with limited support available from AMD.
Product Description
The KCU1250 Characterization Kit provides everything you need to evaluate the 20 GTH 16.3Gbps transceivers available on the UltraScale™ XCKU040-FFVA1156 FPGA. Access to both the Integrated Bit Error Ratio Test (IBERT) demonstration and the Vivado™ Design Suite enables quick evaluation of the industry leading GTH transceivers. Each GTH Quad and its associated reference clock are routed from the FPGA to the BullsEye connector pad. This enables users to connect to a broad range of evaluation platforms, from backplanes and optical evaluation boards to high speed test equipment.
Key Features & Benefits
- Hardware environment for characterizing and evaluating the GTH transceivers on UltraScale XCKU040-2FFVA1156E FPGA
- Hardware, design tools, IP, and pre-verified reference designs
- Integrated Bit Error Ratio Test (IBERT) reference design
- BullsEye connector supporting a full GTH quad, with four transmit/receive pairs
- Five Samtec BullsEye connector pads for the GTH transceivers and reference clocks
- Two pairs of differential MRCC inputs with SMA connectors expand I/O with 3 FPGA Mezzanine Card (FMC) interfaces
Featured AMD Devices
Featuring the ROHS compliant XCKU040-2FFVA1156E FPGA and Dilgilent USB JTAG Programming port
| System Logic Cells (K) | 530 |
|---|---|
| DSP Slices | 1,920 |
| Block RAM (Mb) | 21.1 |
| 16.3Gb/s Transceivers | 20 |
| I/0 Pins | 520 |
Product Information
Board Features
Featuring the Kintex UltraScale KCU1250 Characterization Board
Communication & Networking
- Five Samtec BullsEye connector pads for interfacing to the 20 GTH transceivers and their associated reference clocks
- Two pairs of differential MRCC inputs with SMA connectors
- USB-to-UART bridge
Clocking
- Fixed, 200 MHz 2.5V LVDS oscillator wired to multi-region clock capable (MRCC) inputs
- SuperClock-2 module supporting multiple frequencies
Display
- Power status LEDs
- General purpose DIP switches, LEDs, push buttons, and test I/O
Expansion Connectors
- Three VITA 57.1 FPGA mezzanine card (FMC) high pin count (HPC) connectors
Memory
- SD controller
Power
- PMBus connectivity to on-board digital power supplies
Control & I/O
- I2C Bus
What's Inside
Kintex UltraScale Characterization Board
Featuring the XCKU040-2FFVA1156E FPGA
Vivado™ Design Suite: Design Edition Voucher Code
Node locked & Device-locked to the XCKU040 FPGA, with 1 year of updates
SuperClock-2 Programmable Clock Module
Samtec BullsEye Cable : HDR-155805-01-BEYE
Connects the end users system to the FPGA’s GTH transceivers and reference clocks
Micro USB Cable
Meets all the power requirements UltraScale FPGA GTH transceiver
Mini USB Cable
Power Adapter
MGT Power Modules
Power Cord
Resources
Design Tools
| Name | Description | License Type |
|---|---|---|
| Vivado Design Suite Design Edition | The AMD Vivado™ Design Suite is a revolutionary IP and System Centric design environment built from the ground up to accelerate the design for FPGAs and SoCs. |
Node locked & Device-locked to XCKU040 FPGA, with 1 year of updates |