Yocto Project

• Enable systemd as default init manager on aarch64 architecture
• Disable auto-login (upstream change)
• Remove direct root login (upstream change)
• Versal DFX(single slot) support
• Deprecate usage of BOARD/BOARD_VARIANT in favor of machine inheritance model

PetaLinux

• User must set password for default user on first login
• MicroBlaze lite architecture is deprecated
• Common VCK190 / VMK180 BSP that works with both old and new boards

Device Tree Generator (DTG)

• Automatic generation of AIE clock information.
• DFX single slot support in Versal

AIE Clock Scaling

• At runtime, application or tools can change AIE frequency requirements through the xbutil or XRTAPI
• At runtime, application or tools can get the AI engine frequency through the xbutil or XRTAPI as shown below.
• The AI engine frequency can be scaled down or up
  • Max frequency is restricted to settings defined in the Vivado / Vitis in platform design.
• Use xbutil subcommand advanced to set or get AIE clock frequency

Baremetal Error Handling

• Added the support for reporting AIE errors in baremetal AIE driver
  • Previously only available in Linux
• Baremetal error-handling code can be used as a reference for 3rd-party OS/RTOS porting

• Update to Ubuntu 22.04 LTS (Jammy Jellyfish)
  • https://ubuntu.com/download/xilinx 
• Beta release in mid-May for Kria SOM Kits
• Final release in mid-June for Kria SOM Kits and ZCU10x Evaluation boards
• ZCU10x Image now includes ZCU111 (Zynq UltraScale+ RFSoC)

OpenAMP & LibMetal

• OCM memory can be used for RPMsg between APU & RPU on Zynq UltraScale+ platforms
• OpenAMP & LibMetal synchronized to 2021.10 upstream release
• OpenAMP enabled on Kria SOM platforms

Xen Hypervisor

• Improved VM-to-VM communication mechanisms
• PV drivers support for dom0less VMs
• Dynamic assignment of Programmable Logic blocks to running VMs

• Dynamic Insertion of IDR frame in low latency GOP applications
• VCU processing YUV 4:4:4 10 bit support: Production release
• Custom Xilinx YUV 4:4:4 solution for encode / decode
• Updated V4L2, PS DisplayPort DRM and VCU kernel driver to support Linux v5.15
• Xilinx gstreamer rebased to v1.18.5
• Moved VCU encoder/decoder clock settings to vcu-modules
• Updated VCU device tree node definition with updated clock name sequence and index
• Support for 44.1k & 48k sampled rate audio on PS DisplayPort
  • Compliant with IEC60958

VMK180

• PCIe TRD updated to 2022.1

VCK190

• Quad Sensor Platform: Demonstrate Semantic Segmentation as well as object detection on four video feed from image sensors
• Single Sensor Platform: Demonstrate face detect on video feed coming from image sensor
• HDMI Platform:  Demonstrate 4k image processing using AIE 
• MRMAC Quad Client 4x 10/25G MRMAC Switching Functionality 
• MRMAC IEEE 1588 time stamping

ZCU106 

• Legacy VCU TRDs upgradation to 2022.1 tools
• New design Module: VCU processing YUV 4:4:4 format

• Annual software stack version updates
• Linux kernel 5.15, Yocto Project 3.4 Honister
• Additional device driver support for Kria SOM hardware features
• Ubuntu distribution support updated to 22.04 LTS (Jammy Jellyfish)
• VCU and Multimedia design updates 

Yocto Components

• Update to Yocto Project version 3.2 Gatesgarth release notes https://lists.yoctoproject.org/g/yocto/message/51262
• Jupyterlab update to 3.0.1 and new extension for ipywidgets.
• Integrate OSPI-DM package
• Integrate ACAP cockpit and SOM utilities (xmutil, platformstats, dfx-mgr, ...),
  • See https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM#SOM-Utilities for details.
• fpgamanger_custom / fpgamanager_dtg class updates for PL firmware packaging and deployment

PetaLinux

• The ZynqMP and Versal PetaLinux BSPs boot to tinyram based rootfs and the switch to ext based full rootfs. the default rootfs config is for full rootfs on ext4.
  • ZCU102,ZCU104 and ZCU106 all have now Vitis enabled design and XSA.
  • New ZCU670 BSP is available.
  • PetaLinux tool has distro boot support for MicroBlaze.
  • PetaLinux uses bitbake instead of devtool during config by default.

AI Engine Debugging

• SYSFS nodes for AIE status dump.

FSBL, PLM, and BootGen (Boot)

• PLM support to receive DDR image store from run-time application
• Permission and check for one subsystem to manage lifecycle of other subsystem
• Event management notification support added in different software layers
• Add a CRC value on IPI messaging going to/from the PLM
• XilSecure Client support for bare-metal applications
• Subsystem restart success indication to PLM
• PLM periodic check to ensure PSM is alive
• Boot Image creation wizard for Versal added in Vitis

PLM (Runtime)

• (PLM) NOC runtime clock gating when NOC is not in use
• (PLM) Keepalive with PSM for FuSa
• (PLM) Subscribe/Notify for system errors – enhancements to support with kernel

4U-Boot

• Upgrade to v2021.01
• Block protection commands support in U-Boot for Micron SPI flash devices.
• zynqmp mmio_read and zynqmp mmio_write commands are available to access secure registers from U-Boot.

4Arm Trusted Firmware

• Event management interface support added in ATF
• Arm Trusted Firmware v2.4

Linux

• Update to Linux Kernel - 5.10.x
• VFIO framework support – allow userspace applications to map virtual memory into IOVA addresses
• DMABUF and DMA Fence support – allow userspace applications to directly manage kernel space memory for buffer sharing between applications and drivers
• Rebase patches available

FreeRTOS

• Upgraded FreeRTOS version to 10.4.3

Linux Device Drivers

• Updated AXI Ethernet Driver to support all Linux ethtool features
• Added Linux EDAC driver support for Versal

Bare-Metal Drivers

• Bare-metal driver for AXI Timer (Versal ACAP)
• Change ULPI reset logic in DWC3 driver

Libraries

• Updated open source libraries: binutils (2.35), gcc (10.2), gdb (9.2), glibc (2.32), newlib (3.3), Device Tree Compiler - v1.6.0

Xen Hypervisor

• Updated to Xen Hypervisor - 4.14
• Dynamic assignment of PL blocks (including DMA masters) to new Virtual Machines
  • Program PL at runtime with FPGA Manager, then assign the new blocks to new VMs
• Support for Xen PV drivers in Xen Cache Coloring configurations (PV network, PV block, etc.)
• New Xen user guide. Link: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842530/XEN+Hypervisor.
• PDF format: Xen User Guide

Software Stack Update

• Arm: ATF v.2.4
• Yocto Project: 3.2 Gatesgarth
• Denx: U-boot v2021.01
• Xen: v4.14
• Linux: v5.10.x

Zynq® UltraScale+™ Multimedia and Video Codec Unit

General VCU Updates

• HLG (Hybrid Log Gamma) support in VCU
• Live video pipeline demonstrating Low Latency Phase2 mode @ Ctrl SW
• NTSC Resolution (486i) Enhancement
• Dynamic IDR frame insertion for Pyramidal GOP
• IDR slice type enhancements
• Monochrome (GRAY8/GRAY10) support @ GStreamer
• VCU PL DDR4 Controller IP Enhancements: Provides mechanism to user to add DDR custom part

VCU TRD Designs (ZCU106)

• HLG support Full pipeline
• SDI Rx (HLG) à Encode à Decode à SDI Tx (HLG)

VCU Region of Interest (ROI) TRD (ZCU106)

• Avnet Quadsensor camera input
• Based on Vitis AI v1.4

4Power Advantage Tool: (ZCU111, ZCU208, ZCU216, (ACAP): VCK190, VMK180)

• Expanding the support of Power Advantage Tool to new tool releases, production silicon, and new products
• ACAP Python libraries to integrate power measurement into TRDs and demos

Mixed Security: Disable Lower Security Power Management Master 

• Can disable lower security APU power management for Mixed Security support
• Can disable lower security APU reset
• Integrated tool support via flag selections

Versal Power Domains: FPD, System Power Domain

• Tool and architecture building blocks for Deep Sleep in upcoming release. 

Board Evaluation and Management (BEAM) Tool: VCK190, VMK180

• Out-of-the-box experience. Board configuration and test.
• Easy access to Dev/Demo dashboards: Versal Power Tool, ACAP Cockpit, Power Management Dash (Beta)

Power Advantage Tool (SC): VCK190, VMK180

• Independent from Versal so can be mixed-and-matched with TRDs/Demos/Customer Designs
• Integrated ACAP setup with BEAM Tool, video demo, cut-and-paste Python customization Wiki

ACAP Cockpit (Security updated for public)

• Easy view and editing of Versal registers. Plotting and file features.
• Corresponds with Register documentation.
• Building block for System Controller IP Dashboards.

Power Management Dashboard

• Beta release shows the power state of domains and islands at-a-glance, GUI allows future expansion to Clocks and Performance.
• Independent from Versal so can be mixed-and-matched to view PM state of any Versal application

HSDP/SmartLynq+ EDT and Video

• EDT for SmatLynq+ “System Design Example for High-Speed Debug Port with SmartLynq+ Module
  • https://xilinx.github.io/Embedded-Design-Tutorials/master/docs/index.html

Debug PCIe

• PS High speed debug over PCIe interface  in Early Access.
• PL (Chipscope) High Speed Debug over PCIe Interface in Early access
• PS + PL debug over PCIe Early Access.

Soft Aurora HSDP Example

• Example design released in CED store.
• https://github.com/Xilinx/XilinxCEDStore/tree/2021.1/ced/Xilinx/IPI/hsdp_ced

VCK190 / VMK180 (Versal™)

• VMK180 TRDs
  • VMK180 Multimedia TRD (end June)
  • VMK180 PCIE TRD (end June)
• VCK190
  • VCK190 Ethernet TRD(end July)
  • VCK190 Single Sensor TRD with DPU(end July)
  • VCK190  Quad Sensor TRD with DPU (end July)
  • VCK190 HDMI TRD with AI Tiler and Stitches (end July)

BEAM Tool

• New beta rollout of BEAM Tool (System Controller Image) for VCK190 and VMK180 which includes
  • Power Advantage tool
  • Board Tests
  • Board Configuration
• Production by end September

Zynq UltraScale+ RFSoC

• Updates to RF DC Evaluation Tool for RFSoC Gen1, Gen2 and Gen3
• Updates to PetaLinux BSP for RFSoC Gen1, Gen2 and Gen3
• Production support for RFSoC Gen 3