What is ISIM?
ISim is an abbreviation for ISE Simulator, an integrated HDL simulator used to simulate Xilinx FPGA and CPLD designs.
Can ISE Simulator be used to simulate both RTL and gate-level designs?
Yes, ISE Simulator can be used to simulate both RTL and gate-level designs.
How many configurations of the ISE Simulator are there?
There are two types of configurations for the ISE Simulator; ISE Simulator Lite and the full version of the ISE Simulator. The below information explains how they are delivered:
ISE Design Suite: All Editions: Full version of ISE Simulator : None Limitations in ISE Simulator
ISE WebPACK : ISE Simulator Lite : Performance duration when exceeding 50,000 lines of HDL code
What is ISE Simulator Lite?
ISE Simulator Lite is a limited version of the ISE Simulator. There is only one limitation. When the user design + testbench exceeds 50,000 lines of HDL code, the simulator will start to derate the performance of the simulator for that invocation.
How do I know when I have hit the limit of ISE Simulator Lite?
You will see the following message displayed on the console:
"This is a limited version of the ISE Simulator. The current design has exceeded the design size limit for this version and the performance of the simulation will be derated. Please contact your nearest sales office or visit the Xilinx Online Store if interested in purchasing the full, unlimited version of this simulator"
Is the ISE Simulator supported on PC and Linux platforms?
Yes. The ISE Simulator is supported on the following platforms:
Note: SUSE Enterprise 10 Desktop Server products are binary compatible.
What happens when I hit the line limit of 50,000 lines using ISE Simulator Lite?
The simulator performance would start to derate by 3 - 10X. Much greater degradation will be seen as the line limit continues to increase beyond the 50,000 line limit.
Who can use ISE Simulator most effectively?
Anyone targeting Xilinx FPGAs and CPLDs would be able to simulate using the ISE Simulator.
Are the testbench and library included in the line count?
The line count includes both testbench and source code lines. The Xilinx libraries are not included in the line count.
Can the ISE Simulator be used to simulate designs that are targeted for non-Xilinx devices?
Behavioral Level - All technology-independent RTL can be simulated in ISim Gate Level (or Behavioral designs with technology-specific instantiations) - The ISE Simulator is intended for Xilinx customers only. This is why it comes with Xilinx libraries pre-compiled.
Gate Level (Optional back-annotated timing) - The ISE Simulator is intended for Xilinx customers only. This is why it comes with Xilinx libraries pre-compiled and will only read in the SDF file that is produced by the Xilinx tools.
Can I manually compile a Xilinx library in the ISE Simulator? Is this recommended?
You should never manually compile the Xilinx simulation libraries. Xilinx does not recommend this for the reasons included in the "Gate Level" section. You should use the precompiled libraries.
Does the Embedded Design Kit (EDK) support the ISE Simulator?
Yes. Starting in ISE Design Suite 12, Embedded designs can be simulated in ISE Simulator.
Can I use ISim with AXI Bus Functional Model (BFM)?
Yes. Starting in ISE Design Suite 13, AXI BFM can be simulated with ISim.
How do I get library updates for the ISE Simulator?
ISE Simulator library updates are automatically delivered as part of the ISE updates. There are no special steps required to obtain library updates for the ISE Simulator.
Is there a license needed for the ISE Simulator?
The ISE Simulator follows the same FLEXnet licensing model as other products in the ISE Design Suite.
What is Hardware CoSimulation?
Hardware CoSimulation provides the ability to offload the design or parts of a design to the hardware.
Does Hardware CoSimulation require an additional license?
No it does not, it is included as part of the standard FLEXnet licensing model.
Can I use Hardware CoSimulation with Xilinx WebPack?
Yes you can.
Will all designs see the "50x" performance improvements?
No, this varies from design to design. In general compute intensive designs see the major gains.
What is the meaning of "compute intensive"?
Compute-intensive designs are mainly signal processing designs that do not have a very high I/O bandwidth requirement.
Is there any documentation on the Hardware CoSimulation flow?
Yes, this is included as part of the ISE Simulator User Guide.
Can I use any other interface other than JTAG for Hardware CoSimulation?
Yes,there is support for Ethernet P2P as well, please see the ISE Simulator User Guide for more information.
Is there a User Guide for the ISE Simulator?
Yes the User Guide can be obtained as part of the Software Documentation.
How do I know if I have Lite or the Full version of the ISE Simulator?
Prior to ISE 10.1:
For ISE 10.1:
For ISE Design Suite 11 and later:
Who should I contact if I want to purchase a full version of the ISE Simulator?
Prior to ISE Design Suite 11:
For ISE Design Suite 11 and later:
You can only upgrade from ISE Webpack to one of the ISE Design Suite editions. There is no option to purchase a full version of ISE Simulator only.