Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading partial bit files while the remaining logic continues to operate without interruption. Xilinx Partial Reconfiguration technology allows designers to change functionality on the fly, eliminating the need to fully reconfigure and re-establish links, dramatically enhancing the flexibility that FPGAs offer. The use of Partial Reconfiguration can allow designers to move to fewer or smaller devices, reduce power, and improve system upgradability. Make more efficient use of the silicon by only loading in functionality that is needed at any point in time.
The software approach, introduced in ISE®, introduced in ISE Design Suite version 12.1, represented a new era in Partial Reconfiguration technology. The software tools that unlock the capability to reconfigure a portion of a Xilinx FPGA while the rest of the device remains operational were completely redesigned. This current solution utilizes Partitions, a mature feature that guarantees exact preservation of previously generated results. The PlanAhead design environment can be used to manage design assembly, constraints, implementation and validation.
The Partial Reconfiguration flow in the ISE Design Suite has the following features:
Partial Reconfiguration is available as a product within the ISE Design Suite. Contact your local sales offices for pricing and ordering details.
Professors and researchers associated with universities may receive licenses through the Xilinx University Program (XUP). Learn more about access requirements and procedures for obtaining licenses here.