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Partial Reconfiguration in the ISE Design Suite

Click here for information on Partial Reconfiguration in the Vivado Design Suite

Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading partial bit files while the remaining logic continues to operate without interruption. Xilinx Partial Reconfiguration technology allows designers to change functionality on the fly, eliminating the need to fully reconfigure and re-establish links, dramatically enhancing the flexibility that FPGAs offer. The use of Partial Reconfiguration can allow designers to move to fewer or smaller devices, reduce power, and improve system upgradability. Make more efficient use of the silicon by only loading in functionality that is needed at any point in time.

Partial Reconfiguration Software

The software approach, introduced in ISE®, introduced in ISE Design Suite version 12.1, represented a new era in Partial Reconfiguration technology. The software tools that unlock the capability to reconfigure a portion of a Xilinx FPGA while the rest of the device remains operational were completely redesigned. This current solution utilizes Partitions, a mature feature that guarantees exact preservation of previously generated results.  The PlanAhead design environment can be used to manage design assembly, constraints, implementation and validation.

The Partial Reconfiguration flow in the ISE Design Suite has the following features:

  • Flexible Working Environment
    • PlanAhead™ for GUI support
    • Command line supports existing batch files
    • Black box support, allowing incomplete modules to be omitted
  • User is in Control
    • User decides when to Implement, Import and Export
    • Change implementation options without affecting imported Partitions
    • Floorplan determines what resources are reconfigured
    • Partition information stored in ASCII (xml) file
  • Low level details are handled by the software
    • Tools manage Partition interfaces automatically
    • Design Rule Checks (DRCs) validate design structure and configurations
    • Standard timing closure techniques applied
    • Easily access dedicated silicon features

Partial Reconfiguration is available as a product within the ISE Design Suite. Contact your local sales offices for pricing and ordering details.

Professors and researchers associated with universities may receive licenses through the Xilinx University Program (XUP). Learn more about access requirements and procedures for obtaining licenses here.

Key Technology Benefits

  • Increase solution flexibility by time-multiplexing design functionality
  • Reduce FPGA size or count (and therefore cost) by time-sharing functionality
  • Reduce dynamic power consumption by loading functions on-demand

Key Software Features

  • Supports complete design implementation using robust Partition technology
  • Allows full design constraint entry, timing analysis and verification
  • Supports Virtex-4, Virtex-5, Virtex-6, Virtex-7, Kintex-7, Artix-7 FPGA families and the Zynq™-7000 All Programmable SoC family