The industry's first development tool to automatically generate Triple Module Redundancy (TMR) for space-grade re-programmable FPGAs.

The Triple Module Redundancy (TMR) technology was developed to address the special requirements of FPGAs in high-radiation environments. Designed for space applications and proven through numerous mission-critical projects, TMR provides full SEU and SET immunity for any Virtex®-4 space-grade FPGA design.

Device Family Support

  • Virtex 5QV FPGAs
  • Virtex 4QV FPGAs

System Requirement

  • Windows Server 2000/XP
  • Windows XP Professional
  • Windows 7 Professional

Software Requirements

Key Features

  • Automatically builds TMR into AMD FPGA designs, providing complete SEU and SET immunity
  • Supports all design entry methods, HDLs, and synthesis tools
  • Provides optional SRL16 extraction capability
  • Allows easy integration of custom-built TMR modules
  • Gives designers complete control over how their design is triplicated
  • Increases designer productivity by reducing errors and speeding TMR implementation