Product Description
The JESD204C controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204C. The IP-core supports line speeds up to 32 Gbps per lane and includes full backwards compatibility with JESD204B. The IP core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option. The IP comes with the widest parameter set available and has gone through extensive testing. The IP-core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key ADC/DAC providers and leading Serdes/PHY solutions.
Key Features and Benefits
- Full JESD204C feature set available
- Link and transport layer available
- 8B/10B, 64B/66B, 64B/80B encoding/decoding supported
- Scrambling and de-scrambling included
- Support for all subclasses (0, 1, 2)
- Silicon proven
- Lint/CDC optimized
- UVM regression tested
- Interoperability tested with leading PHY/Serdes vendors
- Solid documentation including integration guide
- Easy to use RTL test environment
- Strong engineering support for bring-up
- Targeting any RTL implementation like ASICs, ASSPs and FPGAs
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VIRTEX-UP Family | XCVU9P | -2 | Vivado 2018.1 | Y | 0 | 80455 | 4 | 2 | 0 | 0 | 490 |
IP Quality Metrics
General Information
| This Data was Current On | Apr 16, 2021 |
| Current IP Revision Number | 2.1.4 |
| Date Current Revision was Released | Apr 08, 2019 |
| Release Date of First Version | Dec 18, 2018 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 10 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Source Code, Netlist |
| Source Code Format(s) | Verilog |
| High-Level Model Included? | N |
| Model Formats | , |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | Verilog |
| Code Coverage Report Provided? | Y |
| Functional Coverage Report Provided? | Y |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Virtex UltraScale+ |
| Software Drivers Provided? | Y |
| Driver OS Support | Linux |
Implementation
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | UltraFast Design Methodology |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Vivado Synthesis |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4-Lite |
| IP-XACT Metadata Included? | Y |
Verification
| Is a Document Verification Plan Available? | Executable and documented plan |
| Test Methodology | Constrained random testing |
| Assertions | N |
| Coverage Metrics Collected | Code |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Synopsys VCS; Mentor ModelSIM |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | VCU118 |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |