TRNG-P200 True Random Number Generator

Product Description

The TRNG-P200 IP core generates reliable physical true random sequences for any FPGA or SoC design targeting cryptographic applications.


Key Features and Benefits

  • AMBA-AXI Interface
  • Internal Fault Detection
  • Passes Diehard Battery of Tests
  • FIPS 140-2 Compliant
  • NIST 800-90B & AIS-31 Health Tests
  • NIST SP800-22 Compliant
  • Passes AIS-31 PTG.2 Test Suites
  • High-quality Entropy Source

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU5P -1 Vivado 2018.2 1180 4653 2 0 0 0 575
Kintex-UP Family XCKU5P -1 Vivado 2018.2 1131 4650 2 0 0 0 575
Spartan-7 Family XC7S50 -2 Vivado 2018.2 1782 4672 2 0 0 0 270
KINTEX-7 Family XC7K70T -2 Vivado 2018.2 1796 4672 2 0 0 0 405
ARTIX-7 Family XC7A50T -2 Vivado 2018.2 1782 4669 2 0 0 0 270
VIRTEX-7X Family XC7VX550T -2 Vivado 2018.2 1859 4669 2 0 0 0 405
Zynq-7000 Family XC7Z030 -2 Vivado 2018.2 1775 4670 2 0 0 0 405
Zynq-7000 Family XC7Z020 -1 Vivado 2018.2 Y 1797 4667 2 0 0 0 212
KINTEX-U Family XCKU040 -2 Vivado 2018.2 1095 4657 2 0 0 0 461
VIRTEX-U Family XCVU080 -2 Vivado 2018.2 1091 4654 2 0 0 0 461

IP Quality Metrics

General Information

This Data was Current On Oct 05, 2020
Current IP Revision Number 602
Date Current Revision was Released Jan 17, 2020
Release Date of First Version Dec 11, 2019

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 3
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? Y
UCFs Provided? XDC
Commercial Evaluation Board Available? N
FPGA Used on Board N/A
Software Drivers Provided? Y
Driver OS Support Linux, Baremetal

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques UltraFast Design Methodology, Inference, Instantiation
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Lite, AXI4-Stream
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology None
Assertions N
Coverage Metrics Collected None
Timing Verification Performed? Y
Timing Verification Report Available N
Simulators Supported Other

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Zedboard
Industry Standard Compliance Testing Passed N
Are Test Results Available? N