Public Key Crypto Core - Elliptic Curve Cryptography (ECC)
- Part Number: PKEC-P521
- Vendor: BERTEN DSP S.L.
- Certified Partner
Product Description
The PKEC-P521 is a Public Key Accelerator IP Core for hardware offloading of Elliptic Curve Cryptography (ECC).
The core implements ECDH Key Exchange, ECDSA, and EC-KCDSA.
It supports ECC operations up to 1008 bits in prime fields, F(p). Any elliptic curve in Short-Weierstrass form can be configured, including NIST, Brainpool, SECG, Curve25519, Curve448, Montgomery, and Twisted-Edwards curves. The PKEC-P521 is compliant with NIST SP800-56A (Rev.3), FIPS 186-5, and ISO 14888-3:2018.
Key Features and Benefits
- AMBA AXI Interface
- Portable to any FPGA or ASIC
- Fault Injection Resistance
- SPA and DPA Countermeasures
- FIPS 186-5 & ISO 14888-3 Compliant
- NIST SP800-56A Compliant
- Curve25519, Curve448
- NIST, SECG, Brainpool Curves
- Prime Fields up to 1008 Bits
- ECDH, ECDSA, EC-KCDSA
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VIRTEX-UP Family | XCVU5P | -1 | Vivado ML 2021.1 | 572 | 2864 | 4 | 0 | 0 | 0 | 420 | |
| Kintex-UP Family | XCKU11P | -1 | Vivado 2018.2 | 537 | 2858 | 4 | 0 | 0 | 0 | 420 | |
| Zynq-UP-MPSoC Family | XCZU2CG | -1 | Vivado 2018.2 | 580 | 2876 | 4 | 0 | 0 | 0 | 420 | |
| Spartan-7 Family | XC7S50 | -2 | Vivado 2018.2 | 978 | 2879 | 4 | 0 | 0 | 0 | 205 | |
| VERSAL_AI_CORE Family | XCVC1802 | -1 | Vivado ML 2021.1 | 604 | 2572 | 4 | 0 | 0 | 0 | 420 | |
| Artix-UP Family | XCAU20P | -2 | Vivado ML 2021.2 | 574 | 2898 | 4 | 0 | 0 | 0 | 475 | |
| KINTEX-7 Family | XC7K70T | -2 | Vivado 2018.2 | 1009 | 2884 | 4 | 0 | 0 | 0 | 305 | |
| ARTIX-7 Family | XC7A50T | -2 | Vivado 2018.2 | 978 | 2879 | 4 | 0 | 0 | 0 | 205 | |
| VIRTEX-7X Family | XC7VX550T | -2 | Vivado ML 2021.1 | 986 | 2889 | 4 | 0 | 0 | 0 | 305 | |
| Zynq-7000 Family | XC7Z030 | -2 | Vivado 2018.2 | 985 | 2874 | 4 | 0 | 0 | 0 | 305 | |
| Zynq-7000 Family | XC7Z020 | -1 | Vivado 2018.2 | Y | 580 | 2876 | 4 | 0 | 0 | 0 | 170 |
| KINTEX-U Family | XCKU040 | -2 | Vivado ML 2021.1 | 547 | 2829 | 4 | 0 | 0 | 0 | 350 | |
| VIRTEX-U Family | XCVU080 | -2 | Vivado ML 2021.1 | 587 | 2856 | 4 | 0 | 0 | 0 | 350 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 04, 2022 |
| Current IP Revision Number | 1.0.210 |
| Date Current Revision was Released | Mar 16, 2022 |
| Release Date of First Version | Mar 16, 2022 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 1 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Netlist |
| High-Level Model Included? | N |
| Integration Testbench Provided | N |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | Y |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | N |
| FPGA Used on Board | N/A |
| Software Drivers Provided? | Y |
| Driver OS Support | Linux, Baremetal |
Implementation
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | UltraFast Design Methodology |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Vivado Synthesis |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4-Lite |
| IP-XACT Metadata Included? | Y |
Verification
| Is a Document Verification Plan Available? | Executable and documented plan |
| Test Methodology | None |
| Assertions | N |
| Coverage Metrics Collected | None |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | N |
| Simulators Supported | Other |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | Zedboard |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |