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  3. ECDH-ECDSA Public Key Crypto Core - Elliptic Curve Cryptography (ECC)

ECDH-ECDSA Public Key Crypto Core - Elliptic Curve Cryptography (ECC)

  • Part Number: PKEC-P521
  • Vendor: BERTEN DSP S.L.
  • Partner Tier: Select Certified
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Product Description

The PKEC-P521 IP Core is a Key Exchange and Digital Signature Accelerator for hardware offloading of Elliptic Curve Cryptography (ECC) in FPGA, SoC, and ASIC technologies.

The core implements ECDH Key Agreement, ECDSA, and EC-KCDSA.

It supports ECC operations up to 1008 bits in prime fields, F(p). Any elliptic curve in Short-Weierstrass form can be configured, including NIST, Brainpool, SECG, Curve25519, Curve448, Montgomery, and Twisted-Edwards curves. The PKEC-P521 is compliant with NIST SP800-56A (Rev.3), FIPS 186-5, and ISO 14888-3:2018.

Key Features and Benefits

  • AMBA AXI Interface
  • Portable to any FPGA or ASIC
  • Fault Injection Resistance
  • SPA and DPA Countermeasures
  • FIPS 186-5 & ISO 14888-3 Compliant
  • NIST SP800-56A Compliant
  • Curve25519, Curve448
  • NIST, SECG, Brainpool Curves
  • Prime Fields up to 1008 Bits
  • ECDH, ECDSA, EC-KCDSA

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU5P -2 Vivado ML 2021.2 561 2808 4 0 0 0 475
Kintex-UP Family XCKU5P -1 Vivado 2018.2 574 2800 4 0 0 0 425
Zynq-UP-MPSoC Family XCZU2CG -1 Vivado 2018.2 593 2802 4 0 0 0 385
Spartan-7 Family XC7S50 -2 Vivado 2018.2 953 2861 4 0 0 0 205
VERSAL_AI_CORE Family XCVC1802 -1 Vivado ML 2021.2 618 2626 4 0 0 0 410
Artix-UP Family XCAU20P -2 Vivado ML 2021.2 594 2802 4 0 0 0 460
KINTEX-7 Family XC7K70T -1 Vivado 2018.2 984 2857 4 0 0 0 230
ARTIX-7 Family XC7A50T -2 Vivado 2018.2 953 2861 4 0 0 0 210
VIRTEX-7X Family XC7VX550T -2 Vivado ML 2021.2 967 2860 4 0 0 0 255
Zynq-7000 Family XC7Z030 -1 Vivado 2018.2 996 2868 4 0 0 0 225
Zynq-7000 Family XC7Z020 -1 Vivado 2018.2 Y 1017 2854 4 0 0 0 170
VIRTEX-U Family XCVU080 -2 Vivado ML 2021.2 586 2808 4 0 0 0 310
KINTEX-U Family XCKU035 -1 Vivado ML 2021.2 583 2799 4 0 0 0 230

IP Quality Metrics

General Information

This Data was Current On Mar 26, 2024
Current IP Revision Number 1.11.259
Date Current Revision was Released May 04, 2023
Release Date of First Version Mar 16, 2022

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 1
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? Y
UCFs Provided? XDC
Commercial Evaluation Board Available? N
FPGA Used on Board N/A
Software Drivers Provided? Y
Driver OS Support Linux, Baremetal

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques UltraFast Design Methodology
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Lite
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology None
Assertions N
Coverage Metrics Collected None
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Other

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Zedboard
Industry Standard Compliance Testing Passed N
Are Test Results Available? N