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Low-Latency 10G Ethernet MAC

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Product Description

The 10G Ethernet MAC IP Core from Fraunhofer Heinrich Hertz Institute is a low latency Ethernet Media Access Controller (MAC) according to IEEE802.3 -2008 specification. The IP Core was specifically designed to have the lowest possible latency, and to be as resource efficient as possible at the same time.

Key Features and Benefits

  • Platform independent core
  • Low Latency, 19.2ns at 64-Bit at 156.25MHz
  • AXI4-Stream protocol support on client transmit and receive interface
  • Low resource usage
  • Deficit Idle Count mechanism to ensure full data rate
  • Padding of short frames (<64 byte)
  • Support for VLAN tagged frames
  • Promiscuous mode support
  • Generation and checking of CRC-32 at full line rate
  • Optional user defined maximum frame length up to 64 kb or complete disabling of frame length check
  • Customization through configuration vector to trade resources for functionality

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU9EG -1 Vivado ML 2022.1 Y 398 1940 912 0 0 0 156

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number 2022.1
Date Current Revision was Released Aug 10, 2022
Release Date of First Version May 22, 2014

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 5
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist, Source Code, Bitstream
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Integration Test Bench Format(s) Verilog
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? N
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq-7000
Software Drivers Provided? N

Implementation

Code Optimized for Xilinx? N
Standard FPGA Optimization Techniques UltraFast Design Methodology
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Other / Vivado 2016.3
Static Timing Analysis Performed? N
AXI Interfaces AXI4-Stream
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Constrained random testing
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Xilinx lSim; Mentor Questa

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ZC706
Industry Standard Compliance Testing Passed N
Are Test Results Available? N