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UDP/IP Offload Engine 10/25G

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Product Description

Chevin Technology’s 10G/25G UDP/IP Ethernet IP core for FPGAs supports high sustained throughput in a compact logic footprint.

The UDP/IP core provides individual port numbers to differentiate between user requests, and receipt of data is verified using the checksum functionality. De-fragmentation is available as an option, to enable large UDP datagrams to be easily sent and received.

Chevin Technology’s 10G/25G UDP/IP Ethernet IP core is configurable for AMD FPGAs and simplifies integration by handling the complete Ethernet frame assembly. The UDP/IP core is a mature product with proven success in customers’ projects and features our patent-pending Authentication Server..

A simple AXI4 streaming interface is all that is required to start sending and receiving UDP datagrams, and only the user data payload is exchanged between the application and the UDP core. For a single port application the port number can be set to a constant, hard coded or software configurable. A multi-port application is supported by the UDP/IP core's AXI4 streaming interface.

Reference designs are available for various boards to assist with integration and we offer our customers bespoke, expert engineering support packages to help meet their project goals.

Key Features and Benefits

  • AXI4s MAC & Application Interfaces
  • Reference Design on AlphaData ADM-PCIE-KU3 board
  • Compose/Decompose complete UDP Datagrams
  • IP frame Checksum Generator/Checker
  • Jumbo frame support up to 32k
  • Configurable operation port filtering
  • 1-64k Ports (configurable ports & filters)
  • Detailed traffic analysis statistics collection
  • Integrated Streaming FIFO – 4 Block RAMs
  • Integrated IP Checksum Generator/Check
  • Flow Control between MAC/User logic
  • Consistently low and predictable latency with zero frame jitter.

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-7 Family XC7V585T -2 Vivado ML 2022.1 Y 0 2508 30 0 0 0 156

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number 4
Date Current Revision was Released Mar 18, 2021
Release Date of First Version Oct 01, 2016

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 5
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist
Source Code Format(s) VHDL
High-Level Model Included? N
Model Formats Other
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Kintex UltraScale
Software Drivers Provided? N
Driver OS Support NA

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Stream
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Constrained random testing
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor ModelSIM; Xilinx lSim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used AlphaData
Industry Standard Compliance Testing Passed N
Are Test Results Available? N