Chevin Technology’s 10G/25G UDP/IP Ethernet IP core for FPGAs supports high sustained throughput in a compact logic footprint.
The UDP/IP core provides individual port numbers to differentiate between user requests, and receipt of data is verified using the checksum functionality. De-fragmentation is available as an option, to enable large UDP datagrams to be easily sent and received.
Chevin Technology’s 10G/25G UDP/IP Ethernet IP core is configurable for AMD FPGAs and simplifies integration by handling the complete Ethernet frame assembly. The UDP/IP core is a mature product with proven success in customers’ projects and features our patent-pending Authentication Server..
A simple AXI4 streaming interface is all that is required to start sending and receiving UDP datagrams, and only the user data payload is exchanged between the application and the UDP core. For a single port application the port number can be set to a constant, hard coded or software configurable. A multi-port application is supported by the UDP/IP core's AXI4 streaming interface.
Reference designs are available for various boards to assist with integration and we offer our customers bespoke, expert engineering support packages to help meet their project goals.
Key Features and Benefits
- AXI4s MAC & Application Interfaces
- Reference Design on AlphaData ADM-PCIE-KU3 board
- Compose/Decompose complete UDP Datagrams
- IP frame Checksum Generator/Checker
- Jumbo frame support up to 32k
- Configurable operation port filtering
- 1-64k Ports (configurable ports & filters)
- Detailed traffic analysis statistics collection
- Integrated Streaming FIFO – 4 Block RAMs
- Integrated IP Checksum Generator/Check
- Flow Control between MAC/User logic
- Consistently low and predictable latency with zero frame jitter.