The Xilinx SmartConnect Technology enables unprecedented levels of performance for the UltraScale+ device portfolio, by solving the system interconnect bottlenecks on high density, multi-million system logic cell designs. In the 2016.1 release of the Vivado® Design Suite HLx Editions, UltraScale+ devices deliver an additional 20-30% performance at high utilization, delivering up to 2X higher performance than 28nm technology devices, without requiring redesign or extra latency insertion.
The SmartConnect Technology includes a system interconnect IP, as well as new optimizations enabled by the UltraScale+ silicon innovations:
The AXI SmartConnect IP: Xilinx’s system connectivity generator, integrating peripherals to the user design. This custom interconnect generates hardware that best matches the user’s system performance requirements, thereby achieving higher system throughput at a lower area and power footprint. The AXI SmartConnect IP is available via Vivado IP Integrator in the 2016.1 release of the Vivado Design Suite.
Time borrowing and useful skew optimization: These optimizations are enabled by the new UltraScale+ fine-grain clock delay insertion capability. These fully automated features mitigate large wire delays and deliver designs running at higher clock frequencies, by shifting available timing slack from the fastest paths to the critical paths of the design.
Pipeline analysis and retiming: These techniques allow designers to further increase performance, by adding extra pipeline stages in the design and applying automatic register retiming optimization.