ChipScope Pro and the Serial I/O Toolkit

ChipScope™ Pro tool inserts logic analyzer, system analyzer, and virtual I/O low-profile software cores directly into your design, allowing you to view any internal signal or node, including embedded hard or soft processors. Signals are captured in the system at the speed of operation and brought out through the programming interface, freeing up pins for your design. Captured signals are then displayed and analyzed using the ChipScope Pro Analyzer tool.

The ChipScope Pro tool also interfaces with your Keysight Technologies bench test equipment through the ATC2 software core. This core synchronizes the ChipScope Pro tool to Keysight’s FPGA Dynamic Probe add-on option. This unique partnership between AMD and Keysight gives you deeper trace memory, faster clock speeds, more trigger options, and system-level measurement capability all while using fewer pins on the FPGA device.

The ChipScope Pro Serial I/O Toolkit provides a fast, easy, and interactive setup and debug of serial I/O channels in high-speed FPGA designs. The ChipScope Pro Serial I/O Toolkit allows you to take bit-error ratio (BER) measurements on multiple channels and adjust high-speed serial transceiver parameters in real-time while your serial I/O channels interact with the rest of the system.

Supported Device Families

ChipScope Pro ChipScope Pro Serial I/O Toolkit
Artix™ 7
Zynq™ 7000
Kintex™ 7 FPGAs (All)
Virtex™ 7 FPGAs (All)
Virtex 6 FPGAs (All)
Virtex 5 FPGAs (All)
Virtex 4 FPGAs (All)
Spartan™ 6 FPGAs (All)
Spartan 3A/3AN/3A DSP/3E/3 FPGAs (All)
Kintex 7 FPGAs, Virtex 6 FPGAs (LXT, SXT, and HXT)
Virtex 7 FPGAs
Virtex 5 FPGAs (LXT, and FXT)
Virtex 4 FPGAs (FX)
Spartan 6 FPGAs (LXT)
  • New RX Margin Analysis tool takes advantage of the Eye Scan feature in 7 Series FPGA transceivers enabling our users to interactively characterize and optimize channel quality in both real time or view the test results offline
  • Analyze any internal FPGA signal, including embedded processor system buses
  • Inserts low-profile, configurable software cores either during design capture or after synthesis
  • All ChipScope Pro cores are available through the AMD CORE Generator™ System
  • Analyzer trigger and capture enhancements makes taking repetitive measurements easy to do
  • Enhancements to the Virtex 5 and Virtex 6 System Monitor console make it easier to access on-chip temperature, voltage, and external sensor data
  • Change probe points without re-implementing the design
  • Debug over a network connection using remote debug, from your office to the lab, or across the globe
  • ChipScope core insertion and generation integrated into Project Navigator and PlanAhead tool flows
  • Add debug probes directly in HDL (VHDL and Verilog) or constraint files
  • Fast and easy interactive setup and debug of FPGA serial I/O channels
  • Measure bit-error ratios (BER) on multiple channels simultaneously
  • Adjust high-speed serial transceiver parameters in real-time while your serial I/O channels are interacting with the rest of the system
  • Built-in pattern generators and checkers, including many standard ITU standard patterns
  • IBERT (Bit Error Ratio Tester) sweep test plot GUI
    • Built-in graphical viewer of IBERT sweep test results for Virtex 6 GTX/GTH FPGA transceivers
    • Standalone graphical viewer for offline analysis of IBERT sweep test results for Kintex 7 FPGA GTX, Virtex 7 FPGA GTX, Virtex 6 FPGA GTX/GTH, Spartan 6 FPGA GTP, and Virtex 5 FPGA GTX transceivers
  • Requires only JTAG port access to your board, no extra pins needed for dedicated high-speed serial debug or setup
  • Support Kintex 7 GTX, and Virtex 7 GTX/GTH/GTZ, and Artix 7 GTP RX Margin Analysis with two different scan algorithms:
    • 2D Full Scan: Scans all horizontal and vertical offset sampling points within the “eye”
    • 1D Bathtub: Scans all horizontal sampling points through the 0 vertical row offset