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Design Preservation is a flow for complex designs that preserves implementation results of a module for use in the next implementation iteration. Often, complex modules in the design are not changing but can be difficult to meet QoR requirements. Repeated time spent on these modules trying to maintain timing is not only frustrating but it is not productive. The Design Preservation flow solves this issue by allowing the customer to meet timing on the critical module(s) of the design and then re-use the implementation results in future iterations. This will reduce the number of implementation iterations while in the timing closure phase of the design and the amount of time in the verification phase.

Design Preservation Software

The Design Preservation flow utilizes Partitions, a mature implementation feature that guarantees exact preservation (down to the routing) of previously generated implementation results.

The Design Preservation flow starts with a synthesis flow that allows each RTL module to be synthesized independently to prevent a design change in one module causing different synthesis results in another module. 3rd party incremental synthesis flows along with the bottom-up synthesis flow (multiple synthesis projects and netlists) are supported. Starting in 13.1, incremental synthesis using XST is supported for the 6 Series and 7 Series devices.

Partitions are added and managed in the PlanAhead design environment or via command line. The entire design is implemented until timing is met on critical modules using existing timing closure techniques. Once timing is met, the key Partitions are exported to an import directory for use in the next iteration. The Partitions technology imports the results by using a ‘copy and paste’ algorithm using the implementation results in the import directory guaranteeing the same timing results. Once the module(s) meets timing, you keep it thereby reducing the number of iterations that are usually required to maintain timing. Also, only the implemented modules have to be verified since the imported modules are guaranteed to have the same timing.

  • Flexible Working Environment
  • PlanAhead™ for GUI support (RTL Projects for 6 Series and 7 Series; Netlist Projects for all FPGA devices)
  • Command line supports existing batch files
  • Chipscope Inserter Support in PlanAhead
  • All of the Design Preservation flow features
  • User is in Control
    • User decides when to Implement, Import and Export
    • Change implementation options without affecting imported Partitions
    • Limited boundary optimizations across Partition boundaries
    • Partition information stored in ASCII (xml) file
  • Easy to Use
    • Extensive DRC messages highlighting ways to improve the design
    • Allows Partitions on a netlist (core) without requiring an RTL wrapper
  • Works with Coregen IP
    • Focusing on PCIe and MIG cores
  • Support complete design implementation using robust Partition technology
  • Supports Spartan®-3, Spartan-6, Kintex®-7, Artix®-7, Zynq-7000, Virtex®-4, Virtex-5, Virtex-6 and Virtex-7 FPGA families
  • Reduce the number iterations in the timing closure phase
  • Reduce the time during verification phase