Power Optimization

ISE™ Design Suite 12 introduces the first automated, intelligent clock-gating technology for FPGA design. With this capability the tool automatically neutralizes unnecessary logic activity, reducing dynamic power usage up to 30%.  A unique set of algorithms automatically identifies and neutralizes unnecessary logic activity, a primary contributor to dynamic power inefficiencies. These algorithms utilize the abundant clock enables (CE) found in the Spartan™ 6 and Virtex™ 6 FPGA. Each CE is ideally suited for power optimization as itconnects to the basic cluster of the slice and controls a small number of registers (only eight). In addition, the algorithms can also utilize the dedicated enables of the BRAM blocks to further reduce dynamic power.

Although the use of clock gating to suppress unnecessary switching in FPGAs is not a new concept, intelligent, fine-grain clock gating is a completely new technology for FPGAs, promising to reduce dynamic power by as much as 30%.

ISE Design Suite 12 is also the only tool that offers intelligent clock gating optimizations integrated with the place-and-route algorithms. These optimizations do not alter the pre-existing logic or the processing of the design, nor do they alter clock placement. The additional logic created is separate from previous logic and only adds 2% LUTs on average to the original design, thus, in the vast majority of cases these optimizations have no affect on timing.