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AMBA AXI4 Interface Protocol

Overview

AMBA® AXI4 (Advanced eXtensible Interface 4) is the fourth generation of the AMBA interface specification from ARM®. Xilinx Vivado Design Suite 2014 and ISE Design Suite 14 extends the Xilinx platform design methodology with the semiconductor industry's first AXI4 Compliant Plug-and-Play IP.

 For customers relying on IP to meet their Time-to-Market requirements for UltraScale, 7-Series, Zynq-7000, Virtex-6 and Spartan-6 based designs, the AXI4 Plug-and-Play IP offers a single standard interface to make IP integration easier. Xilinx offers a broad set of AXI4 based IP with a single open standard interface across the Embedded, DSP, and Logic domains.

Higher Productivity

  • Consolidates broad array of interfaces into one (AXI4), so users only need to know one family of interfaces
  • Makes integrating IP from different domains, as well as developing your own or 3rd party partner IP easier
  • Saves design effort because AXI4 IP are already optimized for the highest performance, maximum throughput and lowest latency

Greater Flexibility

  • Supports Embedded, DSP and Logic Edition users.
  • Tailor the interconnect to meet system goals: Performance, Area, and Power.
  • Enables you to build the most compelling products for your target markets.

Broad IP Availability

Xilinx worked closely with ARM to define the AXI4 specification for high-performance FPGA-based systems and designs. As part of our commitment to AXI4, Xilinx has adopted AXI4 as our next-generation IP interconnect standard for UltraScale, 7-Series, Zynq-7000, Spartan-6, Virtex-6 and future device families going forward

Ecosystem Enablement

3rd party IP and EDA vendors everywhere have embraced the open AXI4 standard, helping to make it a widely adopted interface

  • Cadence Design Systems, Inc., CAST, Inc., Denali Software, Inc., Mentor Graphics Corp., Northwest Logic, OMIINO ltd., Sarance Technologies, Inc., Synopsys, Inc., and Xylon d.o.o. are among those announcing support for IP and tools which support the AXI4 interface
  • This ensures that a strong ecosystem will be in place for building AXI4-based system designs, driving ultimate productivity and faster time to market

Key Documentation

Key Benefits

Key Benefits of AXI4 Interface

Xilinx users will enjoy a wide range of benefits with the transition to AXI4 as a common user interface for IP. AXI4 is:

  • Consistent: All interface subsets use the same transfer protocol
  • Fully specified: Ready for adoption by customers
  • Standardized: Includes standard models and checkers for designers to use
  • Interface-decoupled: The interconnect is decoupled from the interface
  • Extendable: AXI4 is open-ended to support future needs

Additional benefits:

  • Supports both memory mapped and streaming type interfaces
  • Provides a unified interface on IP across communications, video, embedded and DSP functions
  • Is easy to use, with features like automatic pipeline instantiation to help you more easily hit a specific performance target
  • Is equal to or better than current solutions in key attributes, such as fMAX, LUT usage, latency, and bandwidth.
  • Enables Xilinx to efficiently deliver enhanced native memory, external memory interface and memory controller solutions across all application domains

Key Documentation

Details

AXI Details

AXI4

The AXI4 protocol is an update to AXI3 which is designed to enhance the performance and utilization of the interconnect when used by multiple masters. It includes the following enhancements:

  • Support for burst lengths up to 256 beats
  • Quality of Service signaling
  • Support for multiple region interfaces

AXI4-Lite

AXI4-Lite is a subset of the AXI4 protocol intended for communication with simpler, smaller control register-style interfaces in components. The key features of the AXI4-Lite interfaces are:

  • All transactions have a burst length of one
  • All data accesses are the same size as the width of the data bus
  • Exclusive accesses are not supported

AXI4-Stream

The AXI4-Stream protocol is designed for unidirectional data transfers from master to slave with greatly reduced signal routing. Key features of the protocol are:

  • Supports single and multiple data streams using the same set of shared wires
  • Supports multiple data widths within the same interconnect
  • Ideal for implementation in FPGAs

axi4_architecture

Key Documentation