Xilinx builds an array of connectivity solutions to help you design faster. From IP interface solutions that allow you to connect from FPGA to various other chipsets to IP cores that help bridge logic internally within the FPGA, building your design with Xilinx becomes easier and faster. Xilinx also offers several development boards to use together with these IP solutions.
With Ethernet solutions from 1M to 400G, PCI Express® from Gen1x1 to Gen3x16, and a range of other interface IPs that can run up to 25G, we will meet your bandwidth needs.
Listed below are the major IP interface blocks supported by Xilinx. SW drivers accompany many of our IP solutions.
Major IP Interface Blocks Supported by Xilinx
Xilinx offers multiple IP solutions for connecting different IP blocks within the FPGA logic. While there are many different protocols for external interfaces, Xilinx standardizes IP interconnects with the AXI4 protocol.
Both AXI Memory Mapped and AXI Stream can be used for moving data. AXI Memory Mapped is used when address and control must be sent separately with data, and each is sent on its own AXI bus. AXI Stream is used when streaming high speed data with no burst limit and no separate address / control AXI bus. Xilinx also offers AXI Lite for control interfaces.
Latest high speed solution for connecting AXI Memory Mapped interfaces only and exclusively supported in Vivado® IP Integrator. 1
First generation solution that connects AXI Memory Mapped and/or AXI Lite interfaces is supported in RTL and the GUI based Vivado IP Integrator. 1
AXI Stream Interconnect
High speed solution for connecting AXI Stream based interfaces and supported in RTL and the GUI based Vivado IP Integrator. 1
Solution to connect AXI Stream and AXI Memory Mapped interfaces together.
Note 1: Learn more about this solution by watching this Designing with Vivado QuickTake video.
Direct Memory Access (DMA) is a methodology to move data between different locations without the need of a processor to send the data. A typical DMA has a processor or another intelligent controller to set up the source and destination of the data transfer but the DMA block handles the actual transfer of data. Xilinx has a number of DMA IPs built for specific types of data movement. These are set up primarily for the following three areas of use:
|IP Name||DMA for PCIe||AXI DMA||AXI MCDMA||AXI CDMA||ZU+ DMA||AXI VDMA|
|Typical Use Case||Move data between x86 system memory and DDR4 memory attached to FPGA over a PCIe link||Zynq to 10Gb Ethernet communication in programmable logic area||Ethernet (1G/10G) to multiple DDR4 channels||Zynq to BRAM communication in programmable logic area||Zynq to DDR3 communication in processor area||HDMI video data to DDR4 memory for format conversion|
|Interface||PCIe to AXI Memory Mapped or AXI Stream||AXI Stream to AXI Memory Mapped||AXI Stream to (<= 8) AXI Memory Mapped interfaces||AXI Memory Mapped to AXI Memory Mapped||AXI Memory Mapped to Zynq US+ Processor||AXI Stream to AXI Memory Mapped|
|Performance (Gbps)||7GB/s||S2MM: 215
|SW Drivers||x86 based Linux||Linux and Baremetal||Linux and Baremetal||Linux and Baremetal||Linux and Baremetal||Linux and Baremetal|
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The Spartan®-6 FPGA SP605 Evaluation Kit delivers all the basic components of hardware, design tools, IP, and reference designs enabling development right out of the box. This kit provides a flexible environment for system design and provides pre-verified reference design and examples on how to leverage features such as high-speed serial transceivers, PCI Express®, DVI, and/or DDR3. This kit includes an industry-standard FMC (FPGA Mezzanine Card) connector for future scaling and customization to specific applications and markets.