UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

CPRI

Overview

Product Description

The LogiCORE™ CPRI IP core is a high-performance IP solution that implements the Common Public Radio Interface (CPRI). The IP core uses industry leading transceivers to implement the CPRI Physical Layer and provides a compact and customizable Data Link Layer implemented in the FPGA fabric. The CPRI core is ideal for connectivity between Radio Equipment Controllers (REC) or baseband/channel cards and one or more Radio Equipment units (RE). It provides an optimized implementation supporting radio I/Q data, radio unit management, and synchronization in a single efficient protocol.


Key Features and Benefits

  • Designed to CPRI Specification v7.0
  • Can be configured as a master or slave at generation time. Master core can be switched to operate as a slave through a configuration port
  • Suitable for use in both Radio Equipment, Controllers (RECs) and Radio Equipment (RE), including multi-hop systems
  • Easy-to-use interface for in-phase (I) and quadrature-phase (Q) data and synchronization together with optional modules for UMTS terrestrial radio access - frequency division duplexing (UTRA-FDD) and Evolved UMTS Terrestrial Radio Access (E-UTRA) data mappings. interface
  • Supports both Ethernet and HDLC Control and Management channels
  • Supports vendor-specific data transport including support for the passing of control AxC information in global system for mobile communications (GSM) systems
  • Includes the necessary clocking and transceiver logic to enable easy integration into your design
  • Synthesizable example design and simple demonstration test bench provided
  • Delay measurement capability meets CPRI Requirement 21 per CPRI Specification v7.0
  • Optional Reed-Solomon Forward Error Correction (RS-FEC) supported at 8,110.08 Mb/s, 10,137.6 Mb/s, 12,165.12 Mb/s and 24,330.24 Mb/s line rates
  • Optional 100G Ethernet RS-FEC supported at a line rate of either 24,330.24, 12,165.12, 10,137.6 or 8,110.08 Mb/s on selected UltraScale+ devices using GTYE4 transceivers. The Hard FEC can be shared with up to three further CPRI links
  • CPRI core can be converted into a four lane Receiver Hard FEC IP, running at a fixed line rate of either 24,330.24, 12,165.12, 10,137.6 or 8,110.08 Mb/s (on UltraScale+ devices with 100G Ethernet RS-FEC support).
  • CPRI core can support Agnostic Line Coding Aware Mode for 9.8Gbps to 2.45Gbps in 8b10b and all 64b66b line rates in 64bit data width only. Soft FEC and Hard FEC options are also supported for 64b66b line rates.

Table 1: Line Rate Support for 7-Series and UltraScale by speed grade

Line Rate Line Rate 
(Mbps)
7-Series 
GTP
7-Series 
GTX
7-Series 
GTH
UltraScale
GTHE3
GTHE4
UltraScale
GTYE3
GTYE4
    -1 -2 /-3 -1
-2 /-3 -1 -2 /-3 -1lv -1 -2/-3 -1lv -1 -2/-3
Rate 1
614.4
Rate 2 1228.8
Rate 3 2457.6
Rate 4 3072
Rate 5 4915.2  
Rate 6 6144  
Rate 7 9830.4        
Rate 7a 8110.08        
Rate 8 10137.6        
Rate 9 12165.12            
Rate 10 24330.24                     1 2

1 24330.24Mb/s line rate supported on -1 speedgrade on UltraScale+ devices using GTYE4 transceivers.

2 FEC Enabled line rates at 8110.08, 10137.6, 12165.12 and 24330.24Mb/s are available when a 24330.24Mb/s capable core is selected.

Note: Please consult the particular device family Datasheet/User Guide for exact details on configuration options supported.


Resource Utilization


Support

Documentation
Filter Results
Default Default Title Document Type Date
Page Bookmarked