Zynq UltraScale+ RFSoC
The Industry’s Only
Single-Chip Adaptable Radio Platform
Now Extended to Full Sub-6GHz Support
Key Features and Benefits
Integrating a Comprehensive RF Analog-to-Digital Signal Chain
Zynq® UltraScale+™ RFSoCs integrate multi-gigasample RF data converters and soft-decision forward error correction (SD-FEC) into an SoC architecture.
Complete with an Arm® Cortex®-A53 processing subsystem and UltraScale+ programmable logic, the family is the industry’s only single-chip, adaptable radio platform.
Zynq UltraScale+ RFSoC portfolio delivers the right platform for analog, digital, and embedded design, simplifying calibration and synchronization along the signal chain.
The multi-generation portfolio features a breadth of devices with varying direct RF performance to meet diverse spectrum needs and use cases.
Zynq UltraScale+ RFSoC Portfolio
Scalability across the portfolio that meets current and future market needs
4GHz of Max Analog Bandwidth
Breakthough Integration of RF Data Converters on a HW Programmable SoC
- 8x or 16x 6.554GSPS DACs
- 8x 4.096GSPS or 16x 2.058SPS ADCs
5GHz of Max Analog Bandwidth
Timely support of the latest 5G Bands for Regional Deployment
- 16x 6.554GSPS DACs
- 16x 2.220GSPS ADCs
6GHz of Max Analog Bandwidth
Full direct RF support of sub-6GHz bands with extended millimeter wave interface
- 8x or 16x 10.0GSPS DACs
- 8x 5.0GSPS or 16x 2.5GSPS ADCs
5G and LTE Wireless
With Zynq UltraScale+ RFSoCs, wireless infrastructure manufacturers can achieve previously unattainable footprint and power reduction, critical to Massive MIMO deployment.
- Up to 6GHz of direct RF bandwidth for full sub-6GHz 5G New Radio (5G NR) support on a single device
- Device variants with integrated LDPC SD-FEC cores and high DSP density for 5G baseband
- Optimal millimeter wave IF implementations including fixed wireless access and mobile backhaul
Remote-PHY for Cable Access DOCSIS 3.1
Zynq UltraScale+ RFSoC enables cable access multi-service operators (MSOs) to move PHY layer processing closer to home with remote PHY nodes, increasing network capacity.
- RF-Analog for stringent power & form factor constraints
- LDPC to meet DOCSIS 3.1 requirements
- FPGA logic for future-proofing full duplex IP
Phased Array Radar/Digital Array RADAR – Radar On A Chip
As a single-chip TRX solution for scalable, multi-function, phased array radar, the Zynq UltraScale+ RFSoC enables low latency transmit and receive for optimal response time in early warning scenarios.
- Full L-Band Sampling
- Partial S-Band Direct Sampling, full S-Band 2 nd Nyquist
- Partial C-Band Direct Sampling
- Software and hardware reconfigurable
Designers can build high-speed multi-function instruments for signal generation and signal analysis by using direct RF-sampling, highly flexible, reconfigurable logic, and software programmability in Zynq UltraScale+ RFSoC.
Satellite Communications
By leveraging highly integrated RF-DAC/ADC and programmable logic, designers can build complex, high bandwidth connectivity modems with Arm-based processing system for ground stations.
LiDAR
Zynq UltraScale+ RFSoC with integrated data converters coupled with the flexibility and parallelism of adaptable hardware is a unique solution in emerging LiDAR technologies from ADAS to advanced 3D imaging applications.
Direct-RF Signal Chain Features
| ZU21DR | ZU25DR | ZU27DR | ZU28DR | ZU29DR | ||
|---|---|---|---|---|---|---|
| Max. RF input Frequency (GHz) | 4 | |||||
| Decimation / Interpolation | 1x, 2x, 4x, 8x | |||||
| 12-bit RF-ADC | # of ADCs | - | 8 | 8 | 8 | 16 |
| Max Rate (GSPS) | - | 4.096 | 4.096 | 4.096 | 2.058 | |
| 14-bit RF-ADC | # of ADCs | - | - | - | - | - |
| Max Rate (GSPS) | - | - | - | - | - | |
| 14-bit RF-DAC | # of DACs | - | 8 | 8 | 8 | 16 |
| Max Rate (GSPS) | - | 6.554 | 6.554 | 6.554 | 6.554 | |
| SD-FEC | 8 | 0 | 0 | 8 | 0 | |
Programmable Logic
| ZU21DR | ZU25DR | ZU27DR | ZU28DR | ZU29DR | |
|---|---|---|---|---|---|
| System Logic Cells (K) | 930 | 678 | 930 | 930 | 930 |
| DSP Slices | 4,272 | 3,145 | 4,272 | 4,272 | 4,272 |
| Memory (Mb) | 60.5 | 41.3 | 60.5 | 60.5 | 60.5 |
| 33G Transceivers | 16 | 8 | 16 | 16 | 16 |
| PCIe Gen 3x16 | 2 | 1 | 2 | 2 | 2 |
| PCIe Gen3 x16 / Gen4 x8 / CCIX | - | - | - | - | - |
| 100G Ethernet MAC/PCS with RS-FEC | 2 | 1 | 2 | 2 | 2 |
| Maximum I/O Pins | 280 | 347 | 347 | 347 | 408 |
Processing System Features
| ZU21DR | ZU25DR | ZU27DR | ZU28DR | ZU29DR | |
|---|---|---|---|---|---|
| Application Processing Unit | Quad-core Arm® Cortex®-A53 MPCore up to 1.33GHz | ||||
| Real-Time Processing Unit | Dual-core Arm Cortex-R5 MPCore up to 533MHz | ||||
| Embedded and External Memory | 256KB On-Chip Memory w/ECC; External DDR4; DDR3; DDR3L; LPDDR4; LPDDR3; External Quad-SPI; NAND; eMMC | ||||
| High-Speed Connectivity | 4 PS-GTR; PCIe Gen1/2; Serial ATA 3.1; DisplayPort 1.2a; USB 3.0; SGMII | ||||
| General Connectivity | 214 PS I/O; UART; CAN; USB 2.0; I2C; SPI; 32b GPIO; Real Time Clock; Watchdog Timers; Triple Timer Counters | ||||
Direct-RF Signal Chain Features
| ZU39DR | ||
|---|---|---|
| Max. RF input Frequency (GHz) | 5 | |
| Decimation / Interpolation | 1x, 2x, 4x, 8x | |
| 12-bit RF-ADC | # of ADCs | 16 |
| Max Rate (GSPS) | 2.220 | |
| 14-bit RF-ADC | # of ADCs | - |
| Max Rate (GSPS) | - | |
| 14-bit RF-DAC | # of DACs | 16 |
| Max Rate (GSPS) | 6.554 | |
| SD-FEC | 0 | |
Programmable Logic
| ZU39DR | |
|---|---|
| System Logic Cells (K) | 930 |
| DSP Slices | 4,272 |
| Memory (Mb) | 60.5 |
| 33G GTY Transceivers | 16 |
| PCIe Gen 3x16 | 2 |
| PCIe Gen3 x16 / Gen4 x8 / CCIX | - |
| 100G Ethernet MAC/PCS with RS-FEC | 2 |
| Maximum I/O Pins | 408 |
Processing System Features
| ZU39DR | |
|---|---|
| Application Processing Unit | Quad-core Arm® Cortex®-A53 MPCore up to 1.33GHz |
| Real-Time Processing Unit | Dual-core Arm Cortex-R5 MPCore up to 533MHz |
| Embedded and External Memory | 256KB On-Chip Memory w/ECC; External DDR4; DDR3; DDR3L; LPDDR4; LPDDR3; External Quad-SPI; NAND; eMMC |
| High-Speed Connectivity | 4 PS-GTR; PCIe Gen1/2; Serial ATA 3.1; DisplayPort 1.2a; USB 3.0; SGMII |
| General Connectivity | 214 PS I/O; UART; CAN; USB 2.0; I2C; SPI; 32b GPIO; Real Time Clock; Watchdog Timers; Triple Timer Counters |
Direct-RF Signal Chain Features
ZU42DR |
ZU43DR | ZU46DR | ZU47DR | ZU48DR | ZU49DR | ||||
|---|---|---|---|---|---|---|---|---|---|
| Max. RF input Frequency (GHz) | 6 | ||||||||
| Decimation / Interpolation | 1x, 2x, 3x, 4x, 5x, 6x, 8x, 10x, 12x, 16x, 20x, 24x, 40x | ||||||||
| 12-bit RF-ADC | # of ADCs | - |
- | - | - | - | - | ||
| Max Rate (GSPS) | - |
- | - | - | - | - | |||
| 14-bit RF-ADC | # of ADCs | 8 | 2 | 4 | 8 | 4 | 8 | 8 | 16 |
| Max Rate (GSPS) | 2.5 |
5.0 |
5.0 | 2.5 | 5.0 | 5.0 | 5.0 | 2.5 | |
| 14-bit RF-DAC | # of DACs | 8 |
4 | 12 | 8 | 8 | 16 | ||
| Max Rate (GSPS) | 10.0 | 10.0 | 10.0 | 10.0 | 10.0 | 10.0 | |||
| SD-FEC | 0 | 0 | 8 | 0 | 8 | 0 | |||
Programmable Logic
| ZU42DR | ZU43DR | ZU46DR | ZU47DR | ZU48DR | ZU49DR | |
|---|---|---|---|---|---|---|
| System Logic Cells (K) | 489 | 930 | 930 | 930 | 930 | 930 |
| DSP Slices | 1,872 | 4,272 | 4,272 | 4,272 | 4,272 | 4,272 |
| Memory (Mb) | 67.8 | 60.5 | 60.5 | 60.5 | 60.5 | 60.5 |
| 33G GTY Transceivers | 8 | 16 | 16 | 16 | 16 | 16 |
| PCIe Gen3x16 | - | - | - | - | - | - |
| PCIe Gen3 x16 / Gen4 x8 / CCIX | 0 | 2 | 2 | 2 | 2 | 2 |
| 100G Ethernet MAC/PCS with RS-FEC | 0 | 2 | 2 | 2 | 2 | 2 |
| Maximum I/O Pins | 152 | 347 | 360 | 347 | 347 | 408 |
Processing System Features
| ZU42DR | ZU43DR | ZU46DR | ZU47DR | ZU48DR | ZU49DR | |
|---|---|---|---|---|---|---|
| Application Processing Unit | Quad-core Arm® Cortex®-A53 MPCore up to 1.33GHz | |||||
| Real-Time Processing Unit | Dual-core Arm Cortex-R5F MPCore up to 533MHz | |||||
| Embedded and External Memory |
256KB On-Chip Memory w/ECC; External DDR4; DDR3; DDR3L; LPDDR4; LPDDR3; External Quad-SPI; NAND; eMMC |
|||||
| High-Speed Connectivity | 4 PS-GTR; PCIe Gen1/2; Serial ATA 3.1; DisplayPort 1.2a; USB 3.0; SGMII | |||||
| General Connectivity | 214 PS I/O; UART; CAN; USB 2.0; I2C; SPI; 32b GPIO; Real Time Clock; Watchdog Timers; Triple Timer Counters | |||||
Documentation
Tools & Example Designs
A variety of solutions are available for developers to easily evaluate and debug designs on Zynq® UltraScale+™ RFSoCs devices. These solutions consist of tools, IP, and reference designs that enable a wide range of capabilities from performance evaluation to system level debug while the user design is running in hardware.
These tools serve as a platform to effectively configure and monitor Zynq UltraScale+ RFSoC features and accelerate product design cycles.
| Name | Description |
|---|---|
| RF Data Converter Evaluation Tool (ZCU111) | The evaluation tool consists of a reference design for the ZCU111 evaluation board and a custom GUI to configure the operation of the RF Data Converters and evaluate the performance of the RF-ADCs and RF-DACs. |
| RF Analyzer | The RF Analyzer tool provides an easy way to configure and debug RF Data Converters in RFSoC devices on any user board. This tool enables debug capabilities using a simple GUI, interacting seamlessly with the RF Data Converter IP example design implemented on the user board.
The RF Analyzer tool is only supported on the Windows environment. |
| RFSoC Frequency Planning Tool | Interactive Excel spreadsheet that aids in frequency planning for Zynq UltraScale+ RFSoC devices. |
| Zynq UltraScale+ RFSoC demo using PYNQ | With ZCU111 Evaluation kit, this demo implements a wireless solution using PYNQ and Jupyter Notebooks. |
Training
Designing with the Zynq UltraScale+ RFSoC
This OnDemand course provides an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC family with a special emphasis on the Data Converter and Soft-Decision FEC blocks.
Classroom - Designing with the Zynq UltraScale+ RFSoC
Provides an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC family with a special emphasis on the Data Converter and Soft-Decision FEC blocks.
Boards, Kits, and Modules
Visit Zynq UltraScale+ RFSoC Boards, Kits, and Modules for details and to place an order today.
