UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

DMA for PCI Express (PCIe) Subsystem

Product Description

The Xilinx® LogiCORE™ DMA for PCI Express® (PCIe) implements a high performance, configurable Scatter Gather DMA for use with the PCI Express Integrated Block.  The IP provides an optional AXI4-MM or AXI4-Stream user interface.

Key Features & Benefits

  • DMA for PCI Express Subsystem connects to the PCI Express Integrated Block. Both IPs are required to build the PCI Express DMA solution
  • Support for 64, 128, 256, 512-bit datapath for UltraScale+™, UltraScale™ devices.  Support for 64 and 128-bit datapath for Virtex®-7 XT devices
  • Up to 4 host-to-card (H2C/Read) data channels for UltraScale+, UltraScale devices. Up to 2 such channels for Virtex-7 XT devices
  • Up to 4 card-to-host (C2H/Write) data channels for UltraScale+, UltraScale devices. Up to 2 such channels for Virtex-7 XT devices
  • 64-bit source, destination, and descriptor addresses
  • Per channel descriptor bypass for custom descriptor creation
  • Configurable user interface
    • Common AXI4 memory mapped (MM) user interface
    • A separate AXI4-Stream user interface
  • AXI Master interfaces enable PCIe reads and writes to bypass the DMA engine
xilinx-131x43
  • Bundled With: Vivado Design Suite
  • License: Xilinx End User License Agreement

Featured Videos

DMA for PCI Express

Featured Documents