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AXI UART16550

Product Description

The AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the AMBA® (Advance Microcontroller Bus Architecture) AXI (Advanced eXtensible Interface) and provides the controller interface for asynchronous serial data transfer. This soft IP core is designed to connect via an AXI4-Lite interface. The AXI UART 16550 described in this document incorporates features described in the National Semiconductor PC16550D UART with FIFOs Data Sheet.

The National Semiconductor PC16550D data sheet is referenced throughout this document and should be used as the authoritative specification. Differences between the National Semiconductor PC16550D and the AXI UART 16550 data sheet are highlighted in the Specification Exceptions section.

Key Features & Benefits

  • AXI4-Lite interface for register access and data transfers
  • Hardware and software register compatible with all standard 16450 and 16550 UARTs
  • Supports default core configuration for 9600 baud, 8 bits data length, 1 stop bit and no parity
  • Implements all standard serial interface protocols
    • 5, 6, 7 or 8 bits per character
    • Odd, Even or no parity detection and generation
    • 1, 1.5 or 2 stop bit detection and generation
    • Internal baud rate generator and separate receiver clock input
    • Modem control functions
    • Prioritized transmit, receive, line status and modem control interrupts
    • False start bit detection and recover
    • Line break detection and generation
    • Internal loopback diagnostic functionality
    • 16 character transmit and receive FIFOs
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  • Bundled With: Vivado Design Suite
    Embedded Development Kit
  • License: Xilinx End User License Agreement

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