We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!


Product Description

The LogiCORE™ IP AXI Universal Asynchronous Receiver Transmitter (UART) Lite interface connects to the Advanced Microcontroller Bus Architecture (AMBA®) specification’s Advanced eXtensible Interface (AXI) and provides the controller interface for asynchronous serial data transfer. This soft LogiCORE IP core is designed to interface with the AXI4-Lite protocol.

Key Features and Benefits

  • AXI interface is based on the AXI4-Lite specification
  • One transmit and one receive channel (full duplex)
  • 16-character transmit and receive FIFOs
  • Configurable number of data bits (5-8) in a character
  • Configurable parity bit (odd or even or none)
  • Configurable baud rate

Resource Utilization


Featured Documents

Default Default Title Document Type Date
Page Bookmarked