The Xilinx® LogiCORE™ IP UltraScale™ architecture integrated IP core for Interlaken is a scalable chip-to-chip interconnect protocol designed to enable the following for use in select UltraScale architectures:
- The lane logic only mode allows each serial transceiver to be used to build a fully featured Interlaken interface. In devices with 48 serial transceivers, up to 600 Gb/s of total throughput can be sustained.
- The protocol logic supported in each integrated IP core scales up to 150 Gb/s. The Interlaken integrated IP core solution is designed to be compliant with Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
- The integrated IP core implements both the lane logic and protocol logic portions of the specification, which saves approximately 60k+ System Logic Cells per instantiation and uses about 1/8th the power of equivalent soft implementations.
Key Features and Benefits
- A total bandwidth up to 150 Gb/s, available in the following configurations
- Up to 12 lanes at 3.125 Gb/s to 12.5 Gb/s date rate
- Up to 6 lanes x 12.5 Gb/s to 25.78125 Gb/s
- Data striping and de-striping across 1 to 12 lanes
- Lane decommissioning
- Supports both packet and burst interleaved modes