Xilinx Interlaken IP core is based on Sarance Technologies Best-In-Class Intellectual Property
Interlaken is a scalable chip-to-chip interconnect protocol designed to enable transmission speeds from 10Gbps to 600Gbps. The Interlaken specification minimizes the pin and power overhead of chip-to-chip interconnect and features a flexible protocol layer which provides a scalable solution that can be used throughout an entire system. In addition, Interlaken uses two levels of CRC checking and a self-synchronizing data scrambler to ensure data integrity and link robustness. Xilinx Interlaken IP Core based on Sarance Technologies Intellectual Property is optimized for Xilinx Gigabit Transceiver technology and is delivered as a netlist implemented in Virtex FPGA families. The core is compliant with the Interlaken Protocol Definition, Revision 1.2, and offers system designers with a risk-free and quick path for adopting Interlaken as their chip-to-chip interconnect protocol.
In addition to having hardened 150G Interlaken in the UltraScale Architecture, we are also able to support up to 300G Interlaken leveraging the hard 150G lane logic mode. Please refer to the product guide for more information. (Registration is required using company email).
The Xilinx Interlaken IP also supports the AXIe Consortium for Optical Data Interface specification referred to as Jumbo Interlaken. This is targeting a new optical interface standard for measurement equipment.
Key Features and Benefits
- Support for up to 600 Gbps of throughput
- Data striping and de-striping across 1 to 24 lanes
- Programmable BurstMax, BurstMin, BurstShort and MetaFrameSize parameters
- Support for Synchronization, Scrambler State, Diagnostic, and Skip Word Block Types
- Data bus width of 64, 128, 256 or 512, 1024, 1536, or 2048 bits
- Channel-level and link-level flow control mechanism
- Full error checking and recovery as defined by Interlaken specification
- Look-Aside (LA) mode support
- AXIe Consortium ODI Specification support