Xilinx offers HDMI2.1 IP subsystems and HDMI2.0 IP subsystems. HDMI2.1 Subsystems are designed to HDMI2.1 specification and supports earlier HDMI standards with support for FRL and TMDS modes and throughput up to 48Gbps. HDMI2.0 IP subsystems designed to HDMI2.0 specification and supports earlier standards with up to 18 Gbit/s throughput over TMDS signaling.
HDMI2.1 subsystems support Ultrascale+ devices.
HDMI2.0 Subsystems supports Versal ACAP, UltraScale+™, UltraScale and 7-Series Xilinx FPGAs.
To help users in creating video solutions with HDMI interfaces, Xilinx offers prepackaged subsystems for HDMI receive or HDMI transmit. These subsystems integrate commonly used functions with video interfaces such as video timing generation, AXI bridges and optional HDCP function with HDMI controller and work out of the box. These subsystems need additional HDMI GT controller (HDMI2.1) or Video phy controller (HDMI2.0) for physical layer implementation.
The HDMI subsystems are designed to be compliant with the HDMI 2.0 standard and includes the following features:
The HDMI 2.1 subsystems are designed to be compliant with the HDMI 2.1 standard and includes the following features: