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AXI4-Stream Interconnect

Overview

Product Description

Included at no additional charge with Vivado and ISE Design Suite.

Xilinx provides the AXI4-Stream Interconnect core which provides capability to connect multiple master/slave AMBA® AXI4-Stream protocol compliant endpoint IP.

The AXI4-Stream Interconnect is a key Interconnect Infrastructure IP which enables connection of heterogeneous master/slave AMBA® AXI4-Stream protocol compliant endpoint IP. The AXI4-Stream Interconnect routes connection from one or more AXI4-Stream master channels to one or more AXI4-Stream slave channels.


Key Features and Benefits

  • Configurable multiple master to multiple slave (up to 16x16) capable cross-point switch.
  • Arbitrary TDATA byte width conversion.
  • Synchronous and asynchronous clock rate conversion.
  • Configurable data-path FIFO buffers including store and forward (packet) capable FIFOs.
  • Optional register slice at boundaries to ease timing closure.
  • Support for multiple clock domains.

Resource Utilization


Support

Documentation

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