Although Ethernet is known as a networking and system-to-system protocol, it has been adapted to other applications, including the backplane. Ethernet is a popular protocol choice in FPGAs because of its flexibility, reliability, and performance.
Whether you are designing low cost 10/100 Mbps Ethernet applications with Spartan®-6 FPGAs or 400G Ethernet applications with Virtex® UltraScale+™ or Versal™ FPGAs, Xilinx has an Ethernet solution for you.
Implemented in 7-nm technology, the Versal ACAP device incorporates a dynamically switchable 10G, 25G, 40G, 50G and 100G Ethernet MAC and PCS integrated blocks that support all FECs for PAM-4 and NRZ applications. The block also supports high accuracy 1588 hardware timestamping.
|200G / 400G Ethernet||40G/50G/100G Ethernet||10G/25G Ethernet||Gigabit Ethernet||10/100M Ethernet|
|200G/400G Ethernet||Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem||Tri-mode Ethernet Soft IP
(10M - 2500 Mbps)
|AXI Ethernet Lite
UltraScale+ Integrated 100G Ethernet Subsystem
|10G/25G Ethernet Subsystem
||UltraScale Integrated 100G Ethernet Subsystem
|25G RS-FEC||AXI 1G/2.5G Ethernet with optional 1588 Subsystem|
|200G RS-FEC||40G/100G EMAC||25G RS-FEC (Multi-Channel leveraging hard 100G Ethernet RS-FEC)||QSGMII|
|100G KR4/KP4 RS-FEC||10G Ethernet with optional 1588 Subsystem||Ethernet 1G/2.5G Ethernet PCS/PMA or SGMII|
|40G/50G Ethernet Subsystem||10G/25G Ethernet Time Senstive Networking (TSN) Subsystem||100M/1G TSN Subsystem|
|50G RS-FEC||10G EMAC||USXGMII|
|10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation (10GBASE-KR)||1G/10G/25G Switching Ethernet Subsystem|
|10 Gigabit Ethernet PCS/PMA (10GBASE-R)||1G/10G Ethernet Application Note (XAPP1243)|
|IEEE 802.3 Clause 74 FEC|
|1G/10G/25G Switching Ethernet Subsystem|