200G IEEE 802.3bs Reed Solomon Forward Error Correction

Overview

Product Description

The Xilinx® LogiCORE™ 200G IEEE 802.3bs Reed Solomon Forward Error Correction IP core implements the Reed-Solomon Forward Error Correction (RS-FEC) functions within the Physical Coding Sublayer.

Key Features and Benefits

  • IEEE Std. 802.3-2018 TX and RX
  • Support for 200G Ethernet FEC
    • Option to use Virtex® UltraScale+™ GTM transceivers for significant resource reduction
    • Low latency soft IP implementation
  • Dynamic latency reporting
  • Configuration and status bus
  • Supports RS(544,514) KP4 encode and decode
  • Supports symbol error statistics (including per-lane statistics)

Support

Documentation
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