Xilinx offers an integrated 100 Gigabit per second (Gbps) Ethernet Media Access Controller (MAC) and Physical Coding Sublayer (PCS) core for high performance applications. The core is designed to the IEEE 802.3-2012 specification in the latest UltraScale™.
The Xilinx 100 Gbps Ethernet MAC and PCS core provides high-performance interconnect technologies for communications equipment and flexibility in implementing emerging interface standards. The PCS portion of the IP can be configured in CAUI-10 (10 lanes x 10.3125G), CAUI-4 (4 lanes x 25.78125G) or a dynamically switchable CAUI-10 and CAUI-4 mode.
The Xilinx 100 Gbps Ethernet MAC and PCS core also enables optional fee-based features for the IEEE 802.3bj Reed-Solomon Forward Error Correction (RS-FEC) and 100GE Auto-Negotiation/Link Training (AN/LT) IP to enable solutions such as KR4, CR4, SR4, CWDM4, PSM4, or ER4f for high performance applications.
Note: The "Get License" button will only direct you to the Xilinx Product Licensing Site to generate the no charge license for the Hard Xilinx UltraScale Integrated 100G Ethernet Subsystem.
Click on the "Order" button for more information on licensing the 100GE Auto-Negotiation/Link Training, AN/LT and/or 100GE RS-FEC (fee-based feature).
Key Features and Benefits
- Supports 10 lanes x10.3125 CAUI-10, 4 lanes x25.78125G CAUI-4 or dynamically switchable CAUI-4 and CAUI-10 mode
- No charge 100G Ethernet MAC and PCS license key enabled
- Optional fee based soft 100G RS-FEC used for such standards as 100GBASE-SR4/KR4/CR4
- Optional fee based soft 100G AN and LT used for 100GBASE-KR4/CR4
- 1588 1-step and 2-step hardware time stamping
- Allows insertion of custom logic such as RS-FEC between the 100G Ethernet integrated block and GT
- Optional Frame Check Sequence (FCS) checking, adding and deleting
- Priority flow control
- Dynamic and static skew support
- PCS Lane Marker insertion and deletion