XAUI/DXAUI has been depricated as of the 2019.1 release.
No charge paramaterizable core which utilizes the serial I/O transceivers available in the Kintex® UltraScale™, Virtex® UltraScale, Virtex-7, Kintex-7, Artix®-7, Zynq®-7000, Virtex-6, Virtex-5, Virtex-4 FX, Virtex-II Pro and Spartan®-6 to support the XAUI function.
The Xilinx 10 Gigabit Attachment Unit Interface (XAUI) LogiCORE™ IP provides a 4-lane high speed serial interface, providing up to 10 Gigabits per second (Gbps) total throughput. Operating at an internal clock speed of 156.25 MHz, the core includes the XGMII Extender Sublayers (DTE and PHY XGXS), and the 10GBASE-X sublayer, as described in clauses 47 and 48 of IEEE 802.3-2012. In addition, the core supports an optional serial MDIO management interface for accessing the IEEE 802.3-2012 clause 45 management registers. The MDIO interface may be omitted to save logic, in which case a simplified management interface is provided via bit vectors.
The design conforms to the IEEE 802.3ae-2012 standard and includes the following functionality:
The XAUI core is ideally suited to provide high-performance interconnect technologies for communications equipment and facilitate easy interfacing with 10 Gbps transceivers supporting this standard (XENPAK compliant devices, for example).