Xilinx is now part ofAMDUpdated Privacy Policy
  2. Intellectual Property
  3. 400G IEEE 802.3bs Reed Solomon Forward Error Correction

400G IEEE 802.3bs Reed Solomon Forward Error Correction

Order
Overview

Product Description

The Xilinx® LogiCORE™ 400G IEEE 802.3bs Reed-Solomon Forward Error Correction IP core implements the Reed-Solomon Forward Error Correction (RS-FEC) sublayer.

Key Features and Benefits

  • IEEE Std. 802.3bs TX and RX
  • Support for soft 400G Ethernet FEC
    • Optional leveraging hardened RS-FEC in Virtex® UltraScale+™ 58G devices
    • Low latency soft IP implementation
  • Dynamic latency reporting
  • Configuration and status bus
  • Supports RS(544,514) KP4 encode and decode
  • Supports symbol error statistics (including per-lane statistics)

Resource Utilization

Support

Device Family:

Design Tools:

Documentation
Default Default Title Document Type Date