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Team Design is a flow that allows multiple engineers to work in parallel on the same design during synthesis and implementation. As FPGA devices continue to grow, they usually require a team of developers. Not only are multiple engineers developing HDL but a separate engineer might be an integrator responsible for the synthesis and implementation of the entire design. To make matters more challenging, the team is often an international team with different portions of the design developed in different locations and even by different companies. The Xilinx Team Design flow introduced in ISE®14.1 release focuses on solving these challenging issues.

Team Design Software

The Team Design flow utilizes Partitions, an implementation feature that guarantees exact preservation (down to the routing) of previously generated implementation results very similar to the Design Preservation flow. This flow has 3 major steps. These include the initial design setup, team member implementation and assembly of all the team member modules into a final design. The initial design setup provides the framework for all of the team members to be able to implement their portion of the design independently of other team members but in-context with the top level design. At intervals during the design cycle, the entire design can be assembled by using the implementation results of each of the team members.

  • Flexible Working Environment
    • PlanAhead™ for GUI support
    • Command line supports existing batch files
    • Black box support, allowing incomplete modules to be omitted
  • All of the Design Preservation flow features
  • Support complete team design using robust Partition technology
  • Supports Artix™-7, Zynq-7000, Virtex®-7 FPGA families, Virtex-4, Virtex-5, Virtex-6, Kintex™-7, Spartan®-3, and Spartan-6 device families
  • The Team Design flow allows multiple developers to work in parallel on one design
  • Allows early implementation results on 1-2 finished modules. Engineers can start implementing their portion of the design without having to wait on the rest of the team.
  • Easier to fix timing related issues. When a team member is working on meeting timing, they only have to implement their portion of the design. This limits the issues to the smaller portion of the design not only reducing runtime but reducing the number of issues.
  • Provides runtime reduction when making small changes to one module. After the design has converged, only the changed module needs to be implemented. The rest of the design can be preserved.