Xilinx provides a PCI Express Gen3 integrated block for PCI Express® (PCIe) in the Virtex®-7 XT and HT family of FPGAs. The Virtex-7 FPGA solution for PCI Express Gen3 includes all of the necessary components to create a complete solution for PCIe. Delivered through the IP Catalog, the Xilinx IP for Endpoint and Root Port simplifies the design process and reduces time-to-market.
This core combined with Xilinx Targeted Design Platforms, helps customers develop system solutions.
Key Features and Benefits
- Compliant with the PCI Express Base Specification 3.0
- Supported Lane width: x1, x2, x4 and x8
- Fully compliant with PCI Express transaction ordering rules
- Optimal buffering for high bandwidth Direct Memory Access (DMA) applications
- Bandwidth scalability interconnect width
- AXI4-Stream Interface