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ChipScope Pro (IBERT) for Virtex-6 GTH

Overview

Product Description

The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-6 FPGA GTH transceivers is a customizable core that can be used to evaluate and monitor Virtex-6 GTH transceivers. The design includes pattern generators and checkers implemented in FPGA logic, as well as access to the ports and DRP attributes of the serial transceivers. Communication logic is also included, to allow the design to be run-time accessible through JTAG. The IBERT core is a self-contained design, and when it is generated, will run through the entire implementation flow, including bitstream generation.


Key Features and Benefits

  • Provides a communication path between the ChipScope Pro Analyzer software and the IBERT core.
  • Has user-selectable number of Virtex-6 FPGA GTH Transceivers.
  • Each transceiver can be customized for the desired line rate, reference clock rate, reference clock source, and datapath width.
  • Requires a system clock sourced from a pin.

Support

Documentation

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