Digital Clock Manager (DCM) Module

Overview

Product Description

The Digital Clock Manager (DCM) primitive in Xilinx FPGA parts is used to implement delay locked loop, digital frequency synthesizer, digital phase shifter, or a digital spread spectrum. The digital clock manager module is a wrapper around the DCM primitive which allows it to be used in the EDK tool suite.


Key Features and Benefits

  • Wrapper around the FPGA architecture DCM primitive, providing full support for use with the EDK design tools
  • Support both active high and active low reset
  • Configurable BUFG insertion

Support

Documentation

Featured Documents

Default Default Title Document Type Date