The Xilinx SPI-4 Phase 2 core provides a fully compliant Packet-Over-SONET/SDH (POS) solution, which can be quickly integrated into networking systems.
Through user-configurable options, the Xilinx SPI-4.2 core provides ultimate flexibility while seamlessly interoperating with industry leading ASSPs to maximize the data transfer bandwidth. The Xilinx SPI-4.2 core is fully compliant with the OIF's System Packet Interface Level 4 (SPI-4) Phase 2 standard, as well as the SATURN® Development Group's POS-PHY Level 4 (PL4) interface specification.
This IP Core has been discontinued. Effective Date: November 6, 2017