SPI-4 Phase 2 Interface Solutions

  • Status: Discontinued
  • Part Number:

Important Notice:

This IP Core has been discontinued. Effective Date: 11/6/2017

Product Description

Through user-configurable options, the SPI-4.2 core provides ultimate flexibility while seamlessly interoperating with industry leading ASSPs to maximize the data transfer bandwidth. The Xilinx SPI-4.2 core is fully compliant with the OIF's System Packet Interface Level 4 (SPI-4) Phase 2 standard, as well as the SATURN® Development Group's POS-PHY Level 4 (PL4) interface specification.

Key Features and Benefits

  • Up to 700 MHz DDR on SPI-4.2 interface supporting 1.2 Gbps pin pair total bandwidth
  • Supports Static and Dynamic Phase Alignment utilizing ChipSync™ technology
  • Bandwidth optimized source core achieves optimal bus throughput without additional FPGA resources
  • Flexible clocking options utilizing DCM, PMCD, global, and regional clocking resources
  • SelectIO™ technology supports flexible pin assignment
  • Configurable 64-bit or 128-bit user interface, both supporting full bandwidth capabilities
  • Supports unsegmented burst sizes up to 16K
  • Optional continuous DPA window monitoring
  • Optional advanced DPA diagnostics
  • Multiple core support: more than 4 cores can be implemented in a single device
  • Sink and Source cores independently configured through CORE Generator™ system for easy customization
  • Supports 1 to 256 addressable channels with fully configurable SPI-4.2 calendar interface



Featured Documents

Default Default Title Document Type Date