Digital Pre-Distortion Offerings and Software Requirements

Hardware Evaluation Time Out Period * : ~ 4 hrs

SOFTWARE Requirements Table

LogiCORE™ Version   AXI4 Support Supported Device Families
Digital Pre-Distortion (DPD) v9.0 Vivado® 2018.3 AXI4
AXI4-Stream
AXI4-Lite
Zynq® UltraScale+™ RFSoc
Zynq® UltraScale+™ MPSoc
Zynq-7000
v8.1rev1 Vivado 2018.1 AXI4
AXI4-Stream
AXI4-Lite
Zynq UltraScale+ RFSoc
Zynq UltraScale+ MPSoc
Zynq-7000
v8.1 Vivado 2018.1 AXI4
AXI4-Stream
AXI4-Lite
Zynq UltraScale+ RFSoc
Zynq UltraScale+ MPSoc
Zynq-7000
v8.0 Vivado 2016.3 AXI4
AXI4-Stream
AXI4-Lite
Zynq UltraScale+ MPSoc
Zynq-7000
v7.1
Discontinued
(no longer supported)
Vivado 2015.4
AXI4
AXI4-Stream
AXIR-Lite
Zynq-7000
v7.0
Discontinued
(no longer supported)
Vivado 2014.4 AXI4
AXI4-Stream
AXIR-Lite
Zynq-7000
v6.0
Discontinued
(no longer supported)
ISE® 14.3 AXI4-Stream
AXI4-Lite
Zynq-7000
Artix®-7
Kintex®-7 / -2L
Virtex®-7 / XT / -2L
Virtex-6 CXT / LXT / SXT
v5.0
(no longer supported)
ISE 13.2 Legacy Virtex-6 CXT / LXT / SXT
Virtex-5 FXT / SXT / LXT/ TXT / LX

Download the required software from the Xilinx.com Downloads page. For information on New Features, Known Issues, and Patches please refer to the Licensing Solution Center.

* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.

The IP cores in this table will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.