The XPS Interrupt Controller (XPS INTC) concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor. The registers for checking, enabling and acknowledging interrupts are accessed through a slave interface for the Processor Local Bus (PLB V4.6). The number of interrupts and other aspects can be tailored to the target system.
Key Features and Benefits
- 32-bit PLB(V4.6) slave that can be used with 32, 64 or 128-bit buses
- Configurable number of (up to 32) interrupt inputs
- Single interrupt output
- Easily cascaded to provide additional interrupt inputs