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XPS Interrupt Controller

Product Description

The XPS Interrupt Controller (XPS INTC) concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor. The registers for checking, enabling and acknowledging interrupts are accessed through a slave interface for the Processor Local Bus (PLB V4.6). The number of interrupts and other aspects can be tailored to the target system.

Key Features & Benefits

  • 32-bit PLB(V4.6) slave that can be used with 32, 64 or 128-bit buses
  • Configurable number of (up to 32) interrupt inputs
  • Single interrupt output
  • Easily cascaded to provide additional interrupt inputs

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Tools and Device Support

Device Family Support:

Design Tools Support:

xilinx-131x43
  • License: Xilinx End User License Agreement

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