I/O Buffer Information Specification (IBIS)
We recommend the use of IBIS models whenever possible. IBIS models for many devices are often available as free downloads. Using IBIS provides the following:
- Faster simulation speed.
- Elimination of non-convergence.
- Strong support from virtually all EDA vendors.
Learn Why You Should Use IBIS Models for Your Designs
SPICE: Issues with the Traditional Approach
As I/O switching frequencies have increased and voltage levels have decreased, accurate analog simulation of I/Os has become an essential part of modern high-speed digital system design. By accurately simulating the I/O buffers, termination and circuit board traces, you can significantly shorten your time-to-market for new designs. By identifying signal integrity related issues at the beginning of the design cycle, we can reduce the number of board fixes.
SPICE analysis has traditionally been used in areas such as IC design, which requires a high level of accuracy. However, in the PCB and systems domain, the SPICE method has several disadvantages for both the user and the device vendor.
Since SPICE simulations model a circuit at transistor level, they must contain detailed information about the circuit and process parameters. Most IC vendors consider this type of information proprietary and resist making their models available to the public.
Although SPICE simulations are very accurate, simulation speeds are particularly slow for transient simulation analysis, which is often used when evaluating signal integrity performance. In addition, not all SPICE simulators are fully compatible. Default simulator options may also differ with different SPICE simulators. Because some very powerful options control accuracy, convergence and algorithm type, any inconsistent options may produce poor correlation in simulation results across different simulators. Lastly, because SPICE variants exist, models are often incompatible between simulators; they must be extracted for a specific simulator.
IBIS: Benefits of the Alternative
An alternative to SPICE simulation is I/O Buffer Information Specification (IBIS). Intel originally developed IBIS to give customers access to accurate IO buffer models without risking their intellectual property. The IBIS specification is now maintained by the EIA/IBIS Open Forum, with members from many IC and EDA vendors.
The core of the IBIS model consists of a table with current, voltage and timing information. This is very attractive to the IC vendor because the IO internal circuit is treated as a black box. Transistor level information about the circuit and process details is not revealed.
IBIS models simulation speed are much faster than SPICE, with only a slight decrease in accuracy. Non-convergence, a problem with SPICE models and simulators, is eliminated in IBIS simulation. Virtually all EDA vendors presently support IBIS models and they are easy to use. IBIS models for most devices are freely available over the Internet. It is easy to simulate several different manufacturers devices on the same board.
Xilinx provides IBIS models for all current products, which can be easily downloaded from our web site.