The AXI4-Stream Protocol Checker core monitors AXI4-Stream interfaces for protocol violations and provides an indication of which violation occurred.
The checks are synthesizable versions of the System Verilog protocol assertions provided by ARM in the AMBA 4 AXI4, AXI4-Lite, and AXI4-Stream Protocol Assertion User Guide[Ref 2].
Key Features and Benefits
- Supports checking for AXI4-Stream protocol.
- Supports interface widths:
- TDATA width: 1 to 512 bytes
- TUSER width: 0 to 4096 bits
- TID width: 0 to 32 bits
- TDEST width: 0 to 32 bits
- ChipScope Integrated Controller (ICON)
- ChipScope PRO Virtual Input/Output (VIO)
- ChipScope Integrated Logic Analyzer (ILA)
- ChipScope Pro IBERT for Virtex-7 GTX
- ChipScope Pro IBERT for 7 Series GTX
- ChipScope Pro (IBERT) for Virtex-6 GTH
- ChipScope Pro IBERT for Virtex-5 FPGA GTX Transceivers
- ChipScope Pro IBERT for Spartan-6 GTP Transceivers
- Spartan-6 FPGA Embedded Kit
- Virtex-6 FPGA Embedded Kit