AXI4-Stream Protocol Checker
- Bundled With:
- Vivado Design Suite
Product Description
The AXI4-Stream Protocol Checker core monitors AXI4-Stream interfaces for protocol violations and provides an indication of which violation occurred.
The checks are synthesizable versions of the System Verilog protocol assertions provided by ARM in the AMBA 4 AXI4, AXI4-Lite, and AXI4-Stream Protocol Assertion User Guide[Ref 2].
Key Features and Benefits
- Supports checking for AXI4-Stream protocol.
- Supports interface widths:
- TDATA width: 1 to 512 bytes
- TUSER width: 0 to 4096 bits
- TID width: 0 to 32 bits
- TDEST width: 0 to 32 bits
- Supports optional signals:
- TREADY
- TSTRB
- TLAST
- TKEEP
- Programmable messaging levels for simulation operation
- Instrumented to support Vivado Debug Nets and connections to Vivado Logic Analyzer monitoring
Support
Design Tools:
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