Product Description
The AXI BRAM Controller is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK) and Vivado® IP Integrator (IPI) or available as a stand alone core in the Vivado IP Catalog. The core is designed as an AXI endpoint slave IP for integration with the AXI interconnect and system master devices to communicate to local BRAM. The core supports both single and burst transactions to the BRAM and is optimized for performance.
Key Features and Benefits
- AXI4 (memory mapped) slave interface
- Low latency memory controller
- Separate read and write channel interfaces to utilize dual port FPGA BRAM technology
- Configurable BRAM data width (32-, 64-, and 128-bit)
- Supports INCR burst sizes up to 256 data transfers
- Supports WRAP bursts of 2, 4, 8, and 16 data beats
- Supports AXI narrow and unaligned write burst transfers
- Compatible with Xilinx AXI Interconnect
- Reduced footprint option for AXI4-Lite
- Supports both Internal and External modes of BRAM block widths
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