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Partial Reconfiguration Decoupler IP

Product Description

The Partial Reconfiguration (PR) Decoupler IP provides logical isolation capabilities for PR designs.  One or more PR Decoupler cores can be used to make the interface between a Reconfigurable Partition (RP) and the static logic safe from unpredictable activity while partial reconfiguration is occurring.  When active, user-selected signals crossing between the RP and the static logic are driven to user configurable values. When inactive, signals are passed unaltered.  PR Decoupler cores can be connected to the PR Controller IP or custom user controllers to create a complete Partial Reconfiguration management solution.

The PR Decoupler core can be customized for the number of interfaces, type of interfaces, decoupling functionality, status and control.  AXI-based interfaces are natively supported; easily and efficiently enable AXI4-Stream based control, AXI4-Stream based status, or AXI4-Lite based status and control.

Key Features & Benefits

  • Support for all interface types registered in the Vivado® Design Suite, including customer interfaces
  • Multiple interfaces allowed per decoupler
  • Unique decoupling behavior per interface
  • Each interface can have clock domain crossing support
  • Compatible with AXI4-Lite and AXI4-Stream user interfaces
  • Multiple status and control options
  • Connects directly to the Partial Reconfiguration Controller using the signal based control interface
  • Phased decoupling supported
xilinx-131x43
  • Bundled With: Vivado Design Suite
  • License: Xilinx End User License Agreement

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