Versal Adaptive SoC Soft ECC Proxy
- Bundled With:
- Vivado Design Suite
- License: End User License Agreement
Product Description
As technology is evolving, the dynamic random-access memory (DRAM) device size is increasing and the components on the chips are getting smaller. Because of this there is an increase in the electrical or magnetic interference on the DRAM chips. Lower energy particles are able to change the memory cell’s state. These kinds of interferences can cause a single bit of DRAM to spontaneously flip to the opposite state. This can either lead the system to crash or to corrupt data. In addition, applications addressing the functional safety systems require the mitigation of data and address. This is done not only for the failures induced by interferences, but also for those induced by permanent faults like stuck-at and shorts.
Several approaches have been developed to deal with these unwanted bit-flips. One of them is to calculate an error-correction code (ECC) for the data and store it in the DRAM along with the data. The most common ECC, a SECDED Hamming code, allows you to correct single-bit errors and detect double bit errors.
Key Features and Benefits
- Supports AXI4 and AXI4-Lite.
- Configurable data width from 8 to 512. The data width must be power of 2.
- ECC calculation for every data byte.
- Single bit error detection and correction, double bit error detection for every data byte.
- Supports both soft and hard reset.
- Configurable outstanding transaction support up to 64-bits for read channel..
- When ECC is applied, the value of the data width doubles.
- In case of a single-bit error, the bit is corrected along with the correction being notified.
- Supports Two Types of ECC modes: Hamming and HSIAO.
- Error Injection(Single and Double bit error).
- Slave error response incase of Error detection.
- Error Start address capturing in registers.
- Provides error count for both single and double bit errors