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Digital RADAR/EW

Adaptable RFSoCs, SoC, and FPGAs enable Radar/ISR algorithms with the lowest cost and power

Xilinx cutting edge solutions enables today's RADAR and Intelligence, Surveillance, and Reconnaissance (ISR) systems to achieve mission success while future proofing those systems. Unlike the CPU or GPGPU, Xilinx All Programmable SoC's can be reprogrammed not only to change waveforms but algorithms as well utilizing the Programmable Logic. RFSoC, the 16nm MPSoC with monolithic integrated RF Data Converters is essentially a RADAR on a chip or even a DRFM on a chip. Xilinx FPGAs/SoC are the first choice for EW/ISR solutions which offer the best in class SWAPC.

Design Examples Description Device Support

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Featuring 16x16 Channel RF-Analog 

  • 16x 2GSPS 12-bit ADCs
  • 16x 6.4GSPS 14-bit DACs

Remote Radio for M-MIMO

Phased Array EW / Radar


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Beamforming

Adaptive beamforming is the standard for any RADAR system that requires precision tracking and/or guidance in a spectrum contested environment. Xilinx solutions allow the RADAR designers not have to choose between performance and SWAP-C. Xilinx’s SoC solutions are data type agnostic allowing the designers to use any DSP data type (fixed, float, double). This means a complete solution which requires fixed point complex multiply accumulate and adds in fixed precision and matrix inversion using floating point. Xilinx’s SoCs are also Io agnostic, supporting Ethernet, PCIe, Interlaken, SRIO, or any custom interface.

Virtex UltraScale+

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RADAR on a chip

The RFSoC monolithically integrating 16 2GS ADCs and 16 6GS DACs has disrupted the digital RADAR Array world! Designed for coherency, the RFSoC will scale to any RADAR size from 2 elements to 1000’s of elements. The self-contained design is complete with 4200+ DSP, 16 x 32g GTs, ADCs, DACs, Quad A53’s, Internal RAM. Just add antennas, power, clocks and custom RADAR code. Imagine building such a system with discrete components. Not only would it need racks of VPX cards, high power high latency JESD204b data converters but rigorous and costly ADC/DAC layout design

Virtex UltraScale+
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